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A block diagram of the time-delay digital tanlock loop (TDTL). Bold lines represent multi-bit connections.
Source publication
In a previous work we proposed a phase-lock structure called the time-delay digital tanlock loop (TDTL). This digital phase-locked loop (DPLL) performs nonuniform sampling and utilizes a constant time-delay unit instead of the constant 90-degrees phase-shifter used in conventional tanlock structures. The TDTL reduces the complexity of implementatio...
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Citations
... , where δτ represents the unit impulse function. Consequently, R τ0 for τ0 , hence any two samples of this form of noise are uncorrelated and therefore, they are statistically independent (Hussain, 2005; Pomalaza-Raez, 1988; Mehrotra, 2002Figure 27, the TDTL-LPD outperforms the original TDTL for an SNR over 5 dBs. This is due to the fact that the use of the fixed delay block, in the TDTL, increases the phasedetector nonlinearity as the SNR increases. ...
This article presents the architectures, theoretical analyses and testing results of
modified time delay digital tanlock loop (TDTLs) system. The modifications to the
original TDTL architecture were introduced to overcome some of the limitations of
the original TDTL and to enhance the overall performance of the particular
systems. The limitations addressed in this article include the non-linearity of the
phase detector, the restricted width of the locking range and the overall system
acquisition speed. Each of the modified architectures was tested by subjecting the
system to sudden positive and negative frequency steps and comparing its response
with that of the original TDTL. In addition, the performance of all the architectures
was evaluated under noise-free as well as noisy environments. The extensive simulation
results using MATLAB/SIMULINK demonstrate that the new architectures
overcome the limitations they addressed and the overall results confirmed significant
improvements in performance compared to the conventional TDTL system.
... In addition, we further investigate in this chapter the capability of the TDTL in demodulating angle-modulated signals in the presence of additive Gaussian noise. Significant improvement over analog techniques of nearly 20 dB is obtained [104]. This is mainly due to the to its fast locking performance and its less sensitivity to amplitude variation. ...
Digital phase lock loops are critical components of many communication, signal processing and control systems. This book covers various types of digital phase lock loops.
It presents a comprehensive coverage of a new class of digital phase lock loops called the time delay tanlock loop (TDTL). It also details a number of architectures that improve the performance of the TDTL through adaptive techniques that overcome the conflicting requirements of the locking rage and speed of acquisition.
These requirements are of paramount importance in many applications including wireless communications, consumer electronics and others. Digital Phase Lock Loops illustrates the process of converting the TDTL class of digital phase lock loops for implementation on an FPGA-based reconfigurable system.
These devices are being utilized in software-defined radio, DSP-based designs and many other communication and electronic systems to implement complex high-speed algorithms. Their flexibility and reconfigurability facilitate rapid prototyping, on-the-fly upgradeability, and code reuse with minimum effort and complexity.
... In addition, we further investigate in this chapter the capability of the TDTL in demodulating angle-modulated signals in the presence of additive Gaussian noise. Significant improvement over analog techniques of nearly 20 dB is obtained [104]. This is mainly due to the to its fast locking performance and its less sensitivity to amplitude variation. ...
... In addition, we further investigate in this chapter the capability of the TDTL in demodulating angle-modulated signals in the presence of additive Gaussian noise. Significant improvement over analog techniques of nearly 20 dB is obtained [104]. This is mainly due to the to its fast locking performance and its less sensitivity to amplitude variation. ...
... In addition, we further investigate in this chapter the capability of the TDTL in demodulating angle-modulated signals in the presence of additive Gaussian noise. Significant improvement over analog techniques of nearly 20 dB is obtained [104]. This is mainly due to the to its fast locking performance and its less sensitivity to amplitude variation. ...
... In addition, we further investigate in this chapter the capability of the TDTL in demodulating angle-modulated signals in the presence of additive Gaussian noise. Significant improvement over analog techniques of nearly 20 dB is obtained [104]. This is mainly due to the to its fast locking performance and its less sensitivity to amplitude variation. ...
... In addition, we further investigate in this chapter the capability of the TDTL in demodulating angle-modulated signals in the presence of additive Gaussian noise. Significant improvement over analog techniques of nearly 20 dB is obtained [104]. This is mainly due to the to its fast locking performance and its less sensitivity to amplitude variation. ...
... In addition, we further investigate in this chapter the capability of the TDTL in demodulating angle-modulated signals in the presence of additive Gaussian noise. Significant improvement over analog techniques of nearly 20 dB is obtained [104]. This is mainly due to the to its fast locking performance and its less sensitivity to amplitude variation. ...
... In addition, we further investigate in this chapter the capability of the TDTL in demodulating angle-modulated signals in the presence of additive Gaussian noise. Significant improvement over analog techniques of nearly 20 dB is obtained [104]. This is mainly due to the to its fast locking performance and its less sensitivity to amplitude variation. ...
Digital phase lock loops are critical components of many communication, signal processing and control systems. This exciting new book covers various types of digital phase lock loops. It presents a comprehensive coverage of a new class of digital phase lock loops called the time delay tanlock loop (TDTL). It also details a number of architectures that improve the performance of the TDTL through adaptive techniques that overcome the conflicting requirements of the locking rage and speed of acquisition. These requirements are of paramount importance in many applications including wireless communications, consumer electronics and others. Digital Phase Lock Loops then illustrates the process of converting the TDTL class of digital phase lock loops for implementation on an FPGA-based reconfigurable system. These devices are being utilized in software-defined radio, DSP-based designs and many other communication and electronic systems to implement complex high-speed algorithms. Their flexibility and reconfigurability facilitate rapid prototyping, on-the-fly upgradeability, and code reuse with minimum effort and complexity. The practical real-time results, of the various TDTL architectures, obtained from the reconfigurable implementations are compared with those obtained through simulations with MATLAB/Simulink. The material in this book will be valuable to researchers, graduate students, and practicing engineers.
