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A StarT-Voyager node. The application processor (aP), its level two cache controller, DRAM, and memory controller are all standard. In place of the second application processor is our custom network interface unit (NIU). The NIU contains 3 FPGAs (aBIU, sBIU, TxURxU), 1 ASIC (CTRL), two dual-ported banks of SRAM (aSRAM, sSRAM), a single-ported SRAM (clsSRAM), and an embedded processor (sP). The NIU connects the memory bus of the SMP to a high performance interconnection network (Arctic).
Source publication
: This paper describes StarT-Voyager, a machine designed as an experimental platform for research in cluster system communication. The heart of StarT-Voyager is a network interface unit (NIU) that connects the memory bus of a PowerPC-based SMP to the MIT Arctic network. The NIU is highly flexible, with its set of functions easily modified by firmwa...
Context in source publication
Context 1
... StarT-Voyager system consists of an interconnection network and a set of nodes, with one NIU card per node. Each node consists of an unmodified IBM PowerPC 604e-based two-processor card slot SMP. Each node contains a 166MHz 604e processor and 512KB in-line L2 cache card in one processor slot and a StarT-Voyager network interface unit (NIU) in a second processor slot, Figure 2. The 604e is referred to the application processor (aP). The NIU consists of custom hardware, SRAMs, and a 604 microprocessor that is used as an embedded service processor (sP) to execute firmware. The NIU connects to an MIT Arctic network[1], a 160MB/sec/direction/link fat tree network designed and implemented within our research group. It is important to note that the aP uses all of the original SMP's infrastructure, including the memory controller, DRAM, PCI bridge, and so ...
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Citations
... Other projects have also realized the potential benefits of combining features of message passing and shared memory programming. These include hardware projects with support for shared address spaces and high speed networks [26, 27, 2, 3, 31, 28, 35, 5], as well as software projects that provide run-time support for shared memory on hardware built for message passing [32, 16, 10, 25] and those which explicitly combine shared memory and message passing interfaces at the application level [24, 41, 8]. Other approaches have integrated these two mechanisms more tightly and have developed a distinct programming paradigm fo distributed shared memory (DSM) which is implemented in the SHMEM library [38] and the Unified Parallel C language [12]. ...
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