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Multiple reads of the same Flash memory cell with distinct word-line voltages
provide enhanced precision for LDPC decoding. In this paper, the word-line
voltages are optimized by maximizing the mutual information (MI) of the
quantized channel. The enhanced precision from a few additional reads allows
FER performance to approach that of full precisi...
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... paper focuses on the NAND architecture for Flash memory. Fig. 1 shows the configuration of a NAND Flash memory cell. Each memory cell in the NAND architecture features a transistor with a control gate and a floating ...
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... we will see in Section V-C, small differences in mutual information can lead to significant variations in FER. Thus, it is important to understand whether the constrained thresholds studied in Fig. 9 cause a significant reduction in MMI as compared to unconstrained thresholds. Fig. 10 compares the performance of the constrained optimization, which has a single parameter q, and the full unconstrained optimization. As shown in the figure, the benefit of fully unconstrained optimization is insignificant. Fig. 11 shows performance of unconstrained MMI quan- tization on the Gaussian channel model of Fig. 8 for three and ...
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... constrained thresholds studied in Fig. 9 cause a significant reduction in MMI as compared to unconstrained thresholds. Fig. 10 compares the performance of the constrained optimization, which has a single parameter q, and the full unconstrained optimization. As shown in the figure, the benefit of fully unconstrained optimization is insignificant. Fig. 11 shows performance of unconstrained MMI quan- tization on the Gaussian channel model of Fig. 8 for three and six reads for Codes 1 and 2. With four levels, three reads are required for hard decoding. For MLC (four-level) Flash, using six reads recovers more than half of the gap between hard decoding (three reads) and full soft-precision ...
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... that in Fig. 11, the trade-off between performance with soft decoding and performance with hard decoding is even more pronounced. Code 1 is clearly superior with soft decoding but demonstrates a noticeable error floor when decoded with three or six reads. LDPC error floors due to absorbing sets can be sensitive to the quantization precision, occurring ...
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... soft decoding but demonstrates a noticeable error floor when decoded with three or six reads. LDPC error floors due to absorbing sets can be sensitive to the quantization precision, occurring at low precision but not at high precision [27], [28]. Code 1 has small absorbing sets including the (4, 2), (5, 1), and (5, 2) absorbing sets. As shown in Fig. 12 for the (4,2) absorbing set, these absorbing sets can all be avoided by precluding degree-three variable nodes. Code 2 avoids these absorbing sets because it has no degree-3 variable nodes. As shown in Fig. 11, Code 2 avoids the error floor problems of Code ...
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... but not at high precision [27], [28]. Code 1 has small absorbing sets including the (4, 2), (5, 1), and (5, 2) absorbing sets. As shown in Fig. 12 for the (4,2) absorbing set, these absorbing sets can all be avoided by precluding degree-three variable nodes. Code 2 avoids these absorbing sets because it has no degree-3 variable nodes. As shown in Fig. 11, Code 2 avoids the error floor problems of Code ...
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... can extend the MMI analysis of Section III-B to any model for the Flash memory read channel. Consider again the 4-level 6-read MLC as a 4-input 7-output DMC. Instead of assuming Gaussian noise distributions as shown in Fig. 8, Fig. 13 shows the four conditional threshold-voltage proba- bility density functions generated according to the six-month retention model of [16] and the six word-line voltages that maximize MI for this noise model. While the conditional noise for each transmitted (or written) threshold voltage is similar to that of a Gaussian, the variance of ...
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... R to maximize MI, the CR method can be viewed as a constraint that can be applied to MMI optimization to reduce the search space. The CR method can also simplify optimization because, as shown for the single-q constraint in Fig. 9, MI is a quasi-concave function of R in the region of interest for the MLC (four-level) symmetric Gaussian channel. Fig. 14 shows MI as a function of R for MLC (four-level) Flash with six quantization thresholds (seven quantization levels) for both the simple symmetric Gaussian model and the more realistic retention model of [16]. The Gaussian Fig. 15. Mutual information and frame error rate for Code 1 separately plotted as functions of the constant-ratio ...
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... 9, MI is a quasi-concave function of R in the region of interest for the MLC (four-level) symmetric Gaussian channel. Fig. 14 shows MI as a function of R for MLC (four-level) Flash with six quantization thresholds (seven quantization levels) for both the simple symmetric Gaussian model and the more realistic retention model of [16]. The Gaussian Fig. 15. Mutual information and frame error rate for Code 1 separately plotted as functions of the constant-ratio value R for six quantization thresholds (seven levels). Curves are shown for both the 4-PAM Gaussian model with SNR = 13.76 dB and the retention model of [16] for 6 months. These two models both have an MMI of 1.885 bits shown as a ...
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... MMI approach is a way to select quantization levels in the hope of optimizing frame-error-rate (FER) performance. Fig. 14 shows the FER performance as a function of R for both the Gaussian model and the retention model for LDPC Code 2 described in Section IV. The value of R that provides the maximum MI also delivers the lowest FER as a function of R. This lends support to the approach of selecting quantization thresholds to maximize ...
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... constraint to a constant ratio does not appear to adversely affect FER; the lowest FER as a function of R is essentially the same as the FER achieved by unconstrained MMI quantization. The range of MI in Fig. 14 is small (approximately 0.01 bits), but this variation in MI corresponds to more than an order of magnitude of difference in ...
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... illustrate this, we previously introduced Code 1, which has a high error floor under hard decoding due to the presence of numerous small absorbing sets. As shown in Fig. 15, for Code 1, the lowest FER occurs with R = 15 which provides less mutual information than R = ...
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... we examine code performance using the retention model of [16]. Fig. 16 shows frame error rate (FER) plotted versus retention time for Codes 1 and 2 with three reads and with six reads. Code 2 outperforms Code 1 under both three reads (hard decoding) and six ...
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... three-read quantization whose performance is shown in Fig. 16 is standard hard decoding for four-level MLC. We note that in principle, since the retention model is not symmetric, some gain can be achieved by allowing asymmetric thresholds and optimizing these thresholds using MMI even in the three- read case. However, we found those gains to be insignificant in our ...
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... Fig. 16, the Code-2 FER curves for unconstrained-MMI quantization and for R = 7 are indistinguishable. Recall from Fig. 14 that R = 7 both maximizes the mutual information and minimizes frame error rate for Code 2. This was the hoped- for result of MMI optimization, that it would also optimize the true objective of minimizing FER. However, as ...
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... Fig. 16, the Code-2 FER curves for unconstrained-MMI quantization and for R = 7 are indistinguishable. Recall from Fig. 14 that R = 7 both maximizes the mutual information and minimizes frame error rate for Code 2. This was the hoped- for result of MMI optimization, that it would also optimize the true objective of minimizing FER. However, as we saw in Section V-D, if an LDPC code has a high error floor, optimizing the MMI does not necessarily minimize the ...
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... a code with relatively poor performance can perform slightly better with a quantization that does not maximize the mutual information. Indeed, the best FER performance for Code 1 in Fig. 14 for six reads with constant ratio quantization is with R = 15. Note from Fig. 15 that R = 15 provides a smaller mutual information than R = 7, but R = 15 provides the lowest FER for Code ...
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... a code with relatively poor performance can perform slightly better with a quantization that does not maximize the mutual information. Indeed, the best FER performance for Code 1 in Fig. 14 for six reads with constant ratio quantization is with R = 15. Note from Fig. 15 that R = 15 provides a smaller mutual information than R = 7, but R = 15 provides the lowest FER for Code ...
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... in Fig. 16 that for Code 1 with six reads, the MMI quantization performs slightly worse than the R = 15 quantization. Thus we can see that for a weaker code, the MMI approach may not provide the best possible quantization in terms of FER. However, this situation may well be interpreted as an indicator that it may be worth exploring further code ...
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Citations
... To improve the reliability of 3D flash memory system, advanced error correcting codes (ECCs) are essential. Recently, low-density parity-check (LDPC) codes [15] with hard and soft decision decoding have been considered for 3D flash memory [16][17][18]. For LDPC codes with hard-decision decoding (HDD), the performance mainly depends on the raw bit error rate of the flash memory channel [19,20]. ...
... To further improve the error-correction performance, LDPC codes with soft-decision decoding can be employed and its performance heavily depends on the accuracy of channel log-likelihood ratios. Therefore, increasing the number of read-voltage thresholds (i.e., quantization levels) will effectively improve the accuracy of log-likelihood ratios [18,21,22]. However, for flash memory channel, high-precision quantization is not feasible due to the read latency restriction. ...
... Many studies have examined the quantization design for 2D flash memory under limited number of read-voltage levels [2,18,21,[23][24][25]. These prior works optimized the read-voltage thresholds with perfect knowledge of channel information, e.g., the number of P/E cycles and data retention time. ...
As the technology scales down, two-dimensional (2D) NAND flash memory has reached its bottleneck. Three-dimensional (3D) NAND flash memory was proposed to further increase the storage capacity by vertically stacking multiple layers. However, the new architecture of 3D flash memory leads to new sources of errors, which severely affects the reliability of the system. In this paper, for the first time, we derive the channel probability density function of 3D NAND flash memory by taking major sources of errors. Based on the derived channel probability density function, the mutual information (MI) for 3D flash memory with multiple layers is derived and used as a metric to design the quantization. Specifically, we propose a dynamic programming algorithm to jointly optimize read-voltage thresholds for all layers by maximizing the MI (MMI). To further reduce the complexity, we develop an MI derivative (MID)-based method to obtain read-voltage thresholds for hard-decision decoding (HDD) of error correction codes (ECCs). Simulation results show that the performance with jointly optimized read-voltage thresholds can closely approach that with read-voltage thresholds optimized for each layer, with much less read latency. Moreover, the MID-based MMI quantizer almost achieves the optimal performance for HDD of ECCs.
... The research problem will unavoidably fall into the design of an excellent quantizer. In [9], the maximization of mutual information (MMI) was introduced to design the read voltages of the quantizer. An alternate technique, called entropy-based quantization, was presented in [10]. ...
... Our proposed design is more flexible than the entropy technique [10], in which the number of the read voltages can be an odd or an even number. The theoretical and simulation results demonstrate that our read voltages provide better FER performance than the read voltages optimized by the MMI [9] and Entropy [10]. Moreover, the performance evaluation of the LDPC decoder through Monte Carlo simulation is avoided. ...
... For NAND flash memory with a single set of read voltages, we propose to design the read voltages by maximization of the decoding threshold. The theoretical and simulation results demonstrate that our read voltages provide better FER performance than the read voltages optimized by the MMI [9] and Entropy [10]. • Our design of read voltages can support the various LDPC decoders such as belief propagation, min-sum [16], normalized min-sum [17], and offset min-sum algorithms [18]. ...
Low-density parity-check (LDPC) codes play an important role in the reliability enhancement of commercial NAND flash memory. Unfortunately, due to the requirement of the reading speed of NAND flash memory, the LDPC decoder will not obtain the precise soft information to achieve the performance of maximum likelihood decoding. In this work, we use a density evolution (DE) algorithm to reveal the decoding threshold of the LDPC decoder affected by the read voltages. We propose the efficient design of read voltages so that the LDPC decoder has the lowest decoding threshold. Therefore, this method can guarantee that the designed read voltages are suitable for a given LDPC code. Moreover, since we found that the designed read voltages are related to the structure of the LDPC code, the joint design of the read voltages and LDPC code is then proposed to achieve the capacity of NAND flash memory. The simulation results demonstrate that our proposed design significantly improves the frame error rate (FER) performance of NAND flash memory.
... In Fig. 12, we compare P ( m ̸ = m) of BCH codes, proposed scheme based on PBCH codes, and LDPC codes for the SLC flash memories. LDPC codes with column weight four came from [44] and the read levels are chosen to maximize the mutual information [12]. For P ( m ̸ = m) ≈ 10 −5 , the proposed scheme based on PBCH codes is comparable to LDPC code with 2 reads although the read speed performance is the same as LDPC code with 1 read. ...
High-density flash memories suffer from inter-cell interference (ICI) which threatens the reliability of stored data. In order to cope with the ICI problem, we propose a channel coding scheme with channel state information of flash memories (i.e., side information of ICI). This side information is obtained before writing data into flash memories and incorporated during the encoding stage. We show that flash memories under ICI problem can be transformed into the model of memory with defective cells due to the unique asymmetry property between write (page write) and erase (block erase) operations. Then, the channel coding for memory with defective cells is employed to combat ICI. Simulation results support that the proposed scheme with the ICI side information can effectively improve the decoding failure probability.
... However, the log-likelihood-ratio (LLR) information obtained by the uniform quantization scheme is not accurate. In [9], the authors have proposed a "constant ratio (CR)" non-uniform quantization scheme to improve the memory-sensing accuracy. ...
... A read-voltage optimization scheme based on maximum mutual information (MMI) has been also proposed in [9]. However, this scheme obtains the read voltages under the assumption that the codeword length is infinite. ...
... In particular, at PE = 18000, the proposed dynamic write-voltage design scheme achieves a BER of 2.2 × 10 −6 , while the MRD write-voltage design scheme [7], minimum-RBER write-voltage design scheme [2], MCC write-voltage design scheme [6] and the fixed write-voltage design scheme [4] only accomplish the BERs of 1.0 × 10 −5 , 7.5 × 10 −5 , 1.8 × 10 −4 and 2.3 × 10 −3 , respectively. Fig. 6 show the BER performance of the uniform quantization scheme [8], ART quantization scheme [11], CNN-based detection scheme [10], MMI read-voltage quantization scheme [9], entropy-based quantization scheme [2] and proposed read-voltage optimization scheme versus the PE cycles and retention time over an MLC flash memory channel, respectively. As shown, the proposed read-voltage optimization scheme not only slightly outperforms the MMI quantization scheme, but also is significantly superior to the CNN-based detection scheme, the ART quantization scheme, the entropy-based quantization scheme and the uniform quantization scheme. ...
To mitigate the impact of noise and interference on multi-level-cell (MLC) flash memory with the use of low-density parity-check (LDPC) codes, we propose a dynamic write-voltage design scheme considering the asymmetric property of raw bit error rate (RBER), which can obtain the optimal write voltage by minimizing a cost function. In order to further improve the decoding performance of flash memory, we put forward a low-complexity entropy-based read-voltage optimization scheme, which derives the read voltages by searching for the optimal entropy value via a log-likelihood ratio (LLR)-aware cost function. Simulation results demonstrate the superiority of our proposed dynamic write-voltage design scheme and read-voltage optimization scheme with respect to the existing counterparts.
... Temporary storage of fine-grain sampling data requires a larger buffer region in the chip page, thus increasing the chip area. On the other hand, it has to calculate likelihood probability accurately and establish an accurate effective distribution model of threshold voltage of memory cells [6] to generate soft information. No reliable threshold voltage distribution model of NAND Flash Memory has been developed so far. ...
Insuring data reliability on NAND Flash Memory is an important research issue. As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays NAND Flash memory, Low Density Parity Check (LDPC) codes are recently proposed due to their outstanding error correcting capability. In this paper, a novel Channel Coding Scheme concatenated LDPC with BCH NAND Flash Memory is proposed. Firstly a particular LDPC code with low error floor is constructed and BCH codes are used to generate soft information for LDPC codes. Simulation showed that the proposed Channel Coding Scheme obtains the benefit of both overcoming difficulties of soft information generation and the compatiblity with existing BCH code. With the low error floor of constructed LDPC codes, the proposed Channel Coding Scheme can increase P/E cycles of NAND flash memory more significantly comparing the BCH code.
... Due to the high memory density and fabrication tolerances, errors during the readout are becoming more probable, and more sophisticated error correction algorithms are necessary. To improve the error correction performance, soft reading is applied to the flash cell [9][10][11][12]. Low-density parity-check codes (LDPC) are well-suited for flash systems with hard-input or soft-input decoding [10,[13][14][15][16][17]. ...
... To improve the error correction performance, soft reading is applied to the flash cell [9][10][11][12]. Low-density parity-check codes (LDPC) are well-suited for flash systems with hard-input or soft-input decoding [10,[13][14][15][16][17]. However, the error floor of LDPC codes may cause reliability issues for industrial applications, which have to guarantee word error rates below 10 −16 [18]. ...
... We can conclude that the bit labeling impacts the page capacities and consequently the achievable capacity with page-wise read operations. It also determines the latency for the random access performance for the different pages, because a larger number of references requires more read operations [9,10]. Note that it is not possible for a TLC to completely balance the number of reference voltages for all pages. ...
The growing error rates of triple-level cell (TLC) and quadruple-level cell (QLC) NAND flash memories have led to the application of error correction coding with soft-input decoding techniques in flash-based storage systems. Typically, flash memory is organized in pages where the individual bits per cell are assigned to different pages and different codewords of the error-correcting code. This page-wise encoding minimizes the read latency with hard-input decoding. To increase the decoding capability, soft-input decoding is used eventually due to the aging of the cells. This soft-decoding requires multiple read operations. Hence, the soft-read operations reduce the achievable throughput, and increase the read latency and power consumption. In this work, we investigate a different encoding and decoding approach that improves the error correction performance without increasing the number of reference voltages. We consider TLC and QLC flashes where all bits are jointly encoded using a Gray labeling. This cell-wise encoding improves the achievable channel capacity compared with independent page-wise encoding. Errors with cell-wise read operations typically result in a single erroneous bit per cell. We present a coding approach based on generalized concatenated codes that utilizes this property.
... Current studies on LDPC codes for NAND Flash memory mainly cover the finite-geometry construction schemes [5][6], computer search schemes [7], progressive edge growth (PEG) combined QC-LDPC schemes [8], ACE schemes [9], and other construction schemes that seldom consider the code construction at high code rates, which are unsuitable for NAND Flash memory. New construction schemes need to be provided. ...
... Ge et al. [13] explored the MLC NAND flash channel model in a radiated environment and developed a write voltage optimization scheme using this model. Wang et al. [29,30] proposed a method to optimize the selection of Word line voltage by maximizing mutual information, optimizing the accuracy of LLR, and reduced the decoding latency. Luo et al. [24] built an online threshold voltage distribution model, showing the shift of threshold voltage with P/E cycles. ...
Low-density parity-check (LDPC) codes have been widely adopted in NAND flash in recent years to enhance data reliability. There are two types of decoding, hard-decision and soft-decision decoding. However, for the two types, their error correction capability degrades due to inaccurate log-likelihood ratio (LLR) . To improve the LLR accuracy of LDPC decoding, this article proposes LLR optimization schemes, which can be utilized for both hard-decision and soft-decision decoding. First, we build a threshold voltage distribution model for 3D floating gate (FG) triple level cell (TLC) NAND flash. Then, by exploiting the model, we introduce a scheme to quantize LLR during hard-decision and soft-decision decoding. And by amplifying a portion of small LLRs, which is essential in the layer min-sum decoder, more precise LLR can be obtained. For hard-decision decoding, the proposed new modes can significantly improve the decoder’s error correction capability compared with traditional solutions. Soft-decision decoding starts when hard-decision decoding fails. For this part, we study the influence of the reference voltage arrangement of LLR calculation and apply the quantization scheme. The simulation shows that the proposed approach can reduce frame error rate (FER) for several orders of magnitude.
... It is noteworthy that due to the high circuit complexity and power consumption associated with the very high transmission rate requirement, hard-decision decoding, in place of soft-decision decoding, has been widely used in optical communication applications [12]. The same holds in the storage applications, such as nanoscale and flash memories [13], [14]. Therefore, a fast simulation method for accurately estimating a very low target error probability under hard-decision decoding (or the resulting BSCs) is highly desirable. ...
In this paper, we re-examine the classical problem of efficiently evaluating the block and bit error rate performance of linear block codes over binary symmetric channels (BSCs). In communication systems, the maximum likelihood decoding (MLD) bounds are powerful tools to predict the error performance of the coded systems, especially in the asymptotic regime of low error probability (or high signal-to-noise ratio). Contrary to the conventional wisdom, we prove that for BSCs, all bounds based on Gallager’s first bounding technique, including the famous union bound, are not asymptotically tight for all possible choices of the Gallager region. By proposing the so-called input demodulated-output weight enumerating function (IDWEF) of a code, asymptotically tight MLD upper and lower bounds for BSCs are then derived. In many practical scenarios where performance bounds are not applicable (e.g., due to the unavailability of the relevant coding parameters under a given decoder), the Monte Carlo simulation is commonly used despite its inefficiency, especially in the low error probability regime. We propose an efficient importance sampling (IS) estimator by deriving the optimal IS distribution of the Hamming weight of the error vector. In addition, the asymptotic relative saving on the required sample size of the proposed IS estimator over the state-of-the-art counterpart in the recent literature is characterized. Its accuracy in predicting the efficiency of the proposed IS estimator is verified by extensive computer simulation.
... To enhance the reliability of the memory, error correction schemes such as read reference voltage readjustment [12] and error correcting codes (ECC) [13], [14] are applied to NAND flash memory. The memory controller detects the stored data symbol by sensing the voltage level of the cell using read reference voltage. ...
NAND flash memory is becoming smaller and denser to have a larger storage capacity as technologies related to fine processes are developed. As a side effect of high-density integration, the memory can be vulnerable to circuit-level noise such as random telegraph noise, decreasing the reliability of the memory. Therefore, low-density parity-check code that provides multiple decoding modes is adopted in the NAND flash memory systems to have a strong error correcting capability. Conventional static error recovery flow (ERF) applies decoding modes sequentially, and read latency can increase when preceding decoding modes fail. In this paper, we consider a dynamic ERF using machine learning (ML) that predicts an optimal decoding mode guaranteeing successful decoding and minimum read latency and applies it directly to reduce read latency. Due to process variation incurred in the manufacturing of memory, memory characteristics are different by chips and it becomes difficult to apply a trained prediction model to different chips. Training the customized prediction model at each memory chip is impractical because the computational burden of training is heavy, and a large number of training data is required. Therefore, we consider ERF prediction based on reusable ML to deal with varying input and output relationships by chips due to process variation. Reusable ML methods reuse pre-trained model architecture or knowledge learned from source tasks to adapt the model to perform its task without any loss of performance in different chips. We adopt two reusable ML approaches for ERF prediction based on transfer learning and meta learning. Transfer learning method reuses the pre-trained model by reducing domain shift between a source chip and a target chip using a domain adaptation algorithm. On the other hand, meta learning method learns shared features from multiple source chips during the meta training procedure. Next, the meta-trained model reuses previously learned knowledge to fastly adapt to the different chips. Numerical results validate the advantages of the proposed methods with high prediction accuracy in multiple chips. In addition, the proposed ERF prediction based on transfer and meta learning can yield a noticeable reduction in average read latency as compared to conventional schemes.
