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To enhance their performance, various designs of carbon nanotube (CNT) interconnects were analyzed and compared with conventional copper interconnects. To ameliorate the propagation delay of very long interconnect lines, smart buffers are inserted as repeaters along the lines. The existing buffer designs discussed here, including the conventional,...
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This typescript focuses on unraveling the functional performance deterioration issues related to conventional Cu on‐chip nanointerconnecting wires; mainly occurred due to the shrinking of device dimensions. Buffer insertion methodology proves to be an effective approach for designing high‐speed interconnect network but at the cost of power consumpt...
In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) array is presented. The CAM array comprises of address decoders, encoders, data drivers and BCAM cells. Performance analysis is carried for 4X4 BCAM array. Each BCAM cell is designed based on adiabatic logic with optimum CNTFET parameter f...
Citations
... Existing mechanisms that are used to measure delay and power dissipation include equivalent circuit modelling, SPICE simulations, FDTD and MRA models (Khursheed and Khare 2020a, b;Majumder et al. 2014;Mallick 2017, 2021;Khursheed et al. 2019). Recent advancements in optimization algorithms has made it possible to use a metaheuristic approach like particle swarm optimization (PSO), ant colony optimization (ACO), artificial bee colony optimization (ABCO), etc., that are inspired by natural phenomena, such as the behaviour of particles, ants, bees, are used to optimize the interconnect performance. ...
Hybrid copper–single-walled carbon nanotube (Cu–SWCNT) interconnects are gaining attention recently due to their inherent advantages of better conductivity than Cu and ease of fabrication. This work focuses on optimizing propagation delay and power delay product by optimizing the number of segments using particle swarm optimization (PSO) and machine learning (ML) techniques, for the first time. First, a PSO algorithm is deployed to find the optimal number of segments to minimize the delay and power delay product (PDP). Then, a random forest ML (RFML) algorithm is implemented to find the optimal number of segments for interconnect lengths 1000–6000 µm where the computational time is 9.34 ms which is found to be less compared with PSO algorithm which took 796 ms to run. The data obtained from PSO algorithm are used to train the RFML algorithm and its time consumption is validated. It has also been observed that the number of segments is less for Cu–CNT interconnects compared to Cu interconnects.
... 28 So, these results are significant to understand further, the performance of CNT based circuits and driver-interconnect-load models at high temperatures. 29 Lastly, the possibility of electrostatic discharge (ESD) at high temperatures cannot be ruled out if the inter-wire dielectric breakdown happens. 30 This can be true for Cu, Cu-CNT and Cu-Graphene interconnects due to the scattering of electrons at the Cu edges and also due to skin and proximity effects. ...
This article discusses power consumption trends of two geometries of carbon nanotube (CNT) bundle interconnects for very large scale integration applications. Electrostatic and electrothermal field simulations of square and triangular CNT bundle interconnects were done. Two factors viz. power dissipated and peak temperature are extracted and a new figure of merit called power temperature product (PTP) is defined. The PTP is calculated for interconnect lengths ranging from 500 to 2000µm. Results show that both triangular and square CNT bundles have high power withstanding capacity. Triangular CNT bundles have higher PTP when the associate phase changes are ignored.
... Many works are done on design of circuits and interconnects for subthreshold operation (Fan et al., 2019;Karthikeyan & Mallick, 2017;Khursheed et al., 2019a;Sathyakam et al., 2019b). We have earlier designed CNTFET-based driver circuits for high-speed operation of CNT interconnects at subthreshold voltages (Sathyakam et al., 2019b). ...
... Hence, the inter-CNT coupling capacitance and the induced crosstalk is lesser for T-CNT bundles compared to any conventionally proposed CNT bundle geometries. Other repeater insertion mechanisms and subthreshold operation of mixed CNT bundles is also proposed (Khursheed et al., 2019a;Singh & Dhiman, 2019). ...
Signal reliability of Nano-scale interconnects is a major cause of concern at
subthreshold voltages. This paper deals with the subthreshold operation of carbon
nanotube (CNT) bundle interconnects of two different geometries viz. square
CNT bundles (S-CNT) and triangular CNT (T-CNT) bundles. The output
waveforms of the two interconnect geometries is studied to find out the effects of
ON/OFF times and swing on the rising/falling propagation delays and power
dissipated by the interconnects. Six cases of driver/load configurations
comprising of inverter and transmission gates is considered in this study. Results
show that the performance of CNT bundle interconnects is dependent on the
timing and swing of the output waveforms. Also, triangular CNT bundle
interconnects showed better performance in terms of propagation delay and
power dissipated compared to traditionally proposed square CNT bundles.
... DC performance of CNTFET is predicted to be superior to that of ultimately scaled silicon MOSFETs. 29,30 Tables 7 and 8 shows some important parameters of CNTFET model and MOSFET model used in this article. ...
This typescript focuses on unraveling the functional performance deterioration issues related to conventional Cu on‐chip nanointerconnecting wires; mainly occurred due to the shrinking of device dimensions. Buffer insertion methodology proves to be an effective approach for designing high‐speed interconnect network but at the cost of power consumption. Moreover, ramification of too many buffers as repeaters leads to area overhead. Hence an optimized number must be judicially decided. Proposed circuits for buffers are modeled using variable diameter and multi Vt design techniques to balance delay as well as average power consumption. Interconnects designed with conventional Cu interconnect technology are compared with state of art CNT technology at different lengths. Proposed and Existing Buffer circuit architectures are modeled with both CNT and MOS technology to carry out the comparative simulation analysis using varied combination of CNTFET buffer‐CNT interconnect and CMOSFET buffer‐Cu interconnect. Benchmarking with conventional buffer circuits, simulated results illustrates that ProposedBuffer1 saves dynamic power by 89.96%, leakage power by 89%, and offers delay mitigation by 77.5%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 97.53%, but causes delay penalty. All the HSPICE simulations are carried out using Stanford SPICE model for CNT and BSIM4 PTM for MOS at 32 nm.
The manuscript carries out a comprehensive signal integrity analysis for state of art Graphene nano ribbon type interconnects which are paired with buffers as repeaters. For the investigation purpose different types of buffers are inserted in between long interconnect lines. The equivalent semiconductor model is used to evaluate the in-phase, out of phase and also worst case crossed-talked delay of MLGNR interconnects. The simulation results obtained points out that mitigated crossed-talked delay is obtained for local wires whereas the value degrades for global wires. The worst case crosstalk delay in case of nano GNR interconnects using CNTFET buffer repeaters are around 40, 20 and 2% while using FinFET repeaters are around 47, 30 and 20% less than that obtained using conventional Cu interconnects for wire lengths of 200, 600 and 1200 μm correspondingly.KeywordsGraphene ribbonInterconnectEquivalent semiconductor model (ESC)Driver-interconnect-load structure (DIL)Crossed-talked noise
Scaling dimensions of CMOS integrated circuits bring about a technology slowdown for past decades. Novel spintronics based devices have evolved as promising candidate for future generation integrated circuits. This is because of attractive salient features like superior compatibility with existing MOS process technology, high density of integration, unlimited forbearance and excellent information processing. This paper discusses the implementation of XOR logic gate using the spintronics based on domain wall motion (DWM) phenomenon. This dual input XOR gate is ultra-energy-efficient, robust and also compatible with traditional electrical interconnects. The simulated result shows that the implemented gate shows 56% better energy efficiency in comparison with conventional exclusive OR logic gate. Furthermore, simulating a magnetic impeded full adder using the propound gate shows 28% reduced energy dissipation along with 10% enhanced energy-delay product as compared to conventional one.KeywordsSpintronicsCurrent-induced domain wall motionMagnetic tunnel junctionSpin transfer torque
The greatest irony in the development of viable quantum computers is that decoherence limits scalability and has made quantum information states (qubits) fragile. The recent development of Google’s 54-qubit “SYCAMORE”and IBM’s 127-qubit “EAGLE”fully programmable quantum information processors were significant breakthroughs in the quantum world that encouraged the research community to contribute to the achievement of quantum supremacy. Quantum computers are based on quantum mechanics, and their Hamiltonians are unitary in nature, which distinguishes them from classical logic. As a result, Boolean logic is no longer useful in quantum computing. To limit the effect of decoherence in this Noisy Intermediate Scale Quantum System(NISQ), a quantum error correcting code, such as surface code with transversal operator-based fault-tolerant architecture, has been used. BCD-Adder is a popular adder logic used in digital computers and calculators to perform arithmetic operations directly in the decimal number system, with major applications in the finance sector (e.g. payroll and tax processing). Again, majority logic transforms the ripple carry adder into the carry-look-ahead adder. Using the Clifford+T-group, We present a 4-bit majority-based BCD adder with a fault-tolerant quantum circuit for 1-digit decimal numbers.KeywordsBcd adderClifford+TMajority
The locally adopted technique of Chemical-mechanical polishing (CMP) along with various other steps taken in design for manufacturing procedures employed for the fabrication of nano ICs, results in adverse impact on interconnecting wire parameters as well as device features. In order to enhance the manufacturability yield, performance predictability and also for getting the uniform chip layout a propos to prescribed density criteria; dummy fill insertion into layout is a mandatory step of contemporary manufacturing process. Full chip dummy fill is an iterative process which is time consuming and exponentially increases size of GDS. This paper discusses an algorithm which suggests a more sophisticated dummy-fill technique such that it optimizes the total number of metal fill by keeping a tradeoff between the fill requirement and need of design. The proposed algorithm will iterate automatically till a target density is reached with marginal increase to the size of the GDS. MENTOR GRAPHICS SVRF Calibre commands are used to develop the algorithm. PERL scripting is used to run the job automatically. The simulated experimental results points out that the proposed method renders a more balanced metal density distribution while using lesser dummy metal features. Besides this it shows an acceptable timing overhead.
