Figure 1 - uploaded by Poul F. Williams
Content may be subject to copyright.
A 4-bit adder consisting of a full-adder cell and a 4-bit adder cell with four instantiations of the full-adder cell.
Source publication
This paper presents a method for verifying that two hierarchical
combinational circuits implement the same Boolean functions. The key new
feature of the method is its ability to exploit the modularity of the
circuits to reuse results obtained from one part of the circuits in
other parts. We demonstrate the method on large adder and multiplier
circu...
Similar publications
This paper presents a new technique for decomposition and
technology mapping of speed-independent circuits. An initial circuit
implementation is obtained in the form of a netlist of complex gates,
which may not be available in the design library. The proposed method
iteratively performs Boolean decomposition of each such gate F into a
two-input com...
Interconnection planning is becoming an important design issue for
ASICs and large FPGAs. As the technology shrinks and the design density
increases, proper planning of routing resources becomes all the more
important to ensure rapid and feasible design convergence. One of the
most important issues for planning interconnection is the ability to
pre...
The evaluation of a method for test generation for MVL circuits,
based on the notion of full sensitivity, is given. The estimation is
made on the functional level, by establishing a lower bound on the
number of m-valued n-variable functions that are fully sensitive to all
their variables. It is shown, that for practical values of m and n, the
fract...
This paper propose a model for the complexity of Boolean functions with only XOR/XNOR min-terms using back propagation neural networks (BPNNs) applied to binary decision diagrams (BDDs). The developed BPNN model (BPNNM) is obtained through the training process of experimental data using Brain Maker software package. The outcome of this model is a u...
Citations
The use of a data structure called Boolean Expression Diagrams (BED) in the area of formal verification is discussed. The data structure allows fast and efficient manipulation of Boolean formulae. Equivalence checking of combinational circuits is a formal verification problem which translate into tautology checking of Boolean formulae. One can able to preserve much of the structure of the circuit within the Boolean formulae, by using BEDs. This method can be used to calculate approximately the probability of system failure given the failure probabilities of each of the components.
