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This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE...
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... As most environmental signals are analog in nature, data converters are always and will continuously be utilized in modern electronics for the conversion of analog signals to digital and vice versa [1,2]. Recent trends have seen the rise in use of converters applications for AI accelerators, IOT and automotive electronics [3,4]. ...
... The dynamic and futuristic SET based device possesses huge potential in the VLSI industry and need to be investigated extensively. Till date, several researches have been performed in SET related work (Parekh 2013(Parekh , 2019Ionescu 2005, 2006;Durrani 2010;Ono et al. 2010;Ahsan 2018;Chi et al. 2010;Wasshuber 2001;Chen et al. 1995;Yu et al. 2000;Fonseca et al. 1995;Miralaie et al. 2014;Yu et al. 1999;Ghosh et al. 2016;Jain et al. 2015;Uchida et al. 2000;Jia et al. 2004;Willy and Darma 2016;Deyasi and Sarkar 2019;KhademHosseini et al. 2018;Nugraha and Darma 2012;Abdelkrim 2019;Hosseini et al. 2018;Mahapatra et al. 2003Mahapatra et al. , 2004Bounouar et al. 2012;Castro et al. 2018;Castro-González and Sarmiento-Reyes 2014;Dan and Mahapatra 2010;Delwar et al. 2017;Parekh et al. 2012Parekh et al. , 2014Park et al. 2005;Venkataratnam and Goel 2008;Lientschnig et al. 2003;Li et al. 2004Li et al. , 2008Mukherjee et al. 2014aMukherjee et al. , b, 2015Raut 2017;Raut and Dakhole 2016;Raut and Dakhole 2015;Jana et al. 2014;Deng andChen 2012, 2013;Hu et al. 2004;Lee et al. 2007;Ou and Wu 2005;Zhang et al. 2007;Chaudhari and Gautam 2014;Wei et al. 2012;Deng 2011;Amat et al. 2017;Deshpande et al. 2012Deshpande et al. , 2013Prager et al. 2011;González et al. 2012;Das et al. 2010;Tsiolakis et al. 2010a, b;Sui et al. 2011;Tannu and Sharma 2012;Maeda et al. 2012;Sahafi et al. 2013;Hasani et al. 2013;Raut and Dakhole 2014;Mir 2016, 2018;Inokawa et al. 2018;Eskandarian et al. 2018;Patel et al. 2019;Lageweg et al. 2002;Likharev 1999;Tucker 1992;Kim et al. 2003Kim et al. , 2014Kim et al. , 2016Barraud et al. 2018;Erdman et al. 2019;Bai et al. 2018;Karbasian et al. 2015;Dubuc et al. 2008;Sun et al. 2010;Wen et al. 2020;Keyser et al. 2000;Schumacher et al. 2000;Li-Na et al. 2015;Wang et al. 2007;Patel et al. 2018). Consequently, this paper attempts to review and present the researches that have been so far accomplished in the prospective SET based technology. ...
... , summation circuit(Raut and Dakhole 2016), BCD adder(Mukherjee et al. 2015), 4-bit parallel adder/ subtractor, 4-bit ALU(Raut and Dakhole 2015), reversible logic based ALU, multiplier(Deng and Chen 2013), DAC(Hu et al. 2004), ADC(Lee et al. 2007;Ou and Wu 2005), voltage controlled ring oscillator(Zhang et al. 2007), frequency multiplier(Deng and Chen 2012) and hybrid memory cell(Chaudhari and Gautam 2014;Wei et al. 2012;Mahapatra and Ionescu 2005), have been implemented. Research work inDeng (2011) shows hybrid MOS and SET architectures towards arithmetic applications. ...
Integrated circuit (IC) technology has grown tremendously over the last few decades. The prime goal has been to achieve low-power and high-performance in logic and memory devices with minimal footprint. This has lead to continuous scaling of devices and interconnects over silicon chips. Scaling of technology plays an important role for improvement of IC performance in terms of delay, signal-integrity and power-dissipation. Novel devices like FinFET, nano-electromechanical systems, graphene-FETs and single-electron transistor (SET) offer several advantages over various shortcomings of scaling. The future of IC industry is proposed to be heterogeneous 3D integration of different technologies. A SET is a potential nano device that works on quantum mechanical principle and can be co-integrated with the widely adopted complementary metal-oxide semiconductor technology to enhance its performance at scaled technology nodes. To explore the feasibility of SET, an extensive literature review has been carried out in this paper. The literature review comprises comprehensively research work related to SET theory, design and fabrication. Also, the SET based computing system design is presented for room temperature operation. The extensive literature review and thereafter execution of varying analyses reveal that the SET is a potential nano-device for futuristic applications.
... The compatibility of SET-CMOS integrated logic operation at 22 nm is shown in [9]. Using this concept several block-level designs such as logic circuits [10,11], ADC and DAC [12][13][14], voltage-controlled ring oscillator [15], multiplier [16], 4-bit arithmetic and logic unit (ALU) [17] have been designed. These studies have been performed at individual block level. ...
Over the past several decades, the performance of existing complementary metal oxide semiconductor (CMOS) technology has been improved by scaling of the CMOS transistors size. However, the performance of nanometre scale CMOS‐based designs is limited due to the short‐channel effect and process variation. The single electron transistor (SET) is a promising advanced nanometre scale device that can mitigate these grave issues. In this study, a novel SET‐based computing system is designed and simulated at a supply voltage of 0.8 V, so that it can be 3D integrated with existing CMOS technology. The SET design parameters are considered based on SET fabricated by nanodamascene process for room temperature operation. The computing system works at frequency of 5 GHz with 2.522 μW power dissipation considering interconnect parasites. The frequency and power dissipation of the SET‐based design is nearly 5 times better and 1.6 times lower than for the same design using 16 nm CMOS technology. The results and various analyses show that the SET‐based systems are highly efficient and hence very effective to incorporate in next‐generation very large scale integration designs. The SET‐based design can be also 3D stacked in tandem with existing CMOS technology to achieve higher benefits in terms of speed, power, density, footprint, and functionality.
... Mastering of technology at this size range has the ability to customize any doable type of materials the way we need. The SET technology is the greatest emerging technology accepted to meet the required features and to replace the current CMOS technology [9][10][11]. SET based devices and circuits have received enormous attention in the research community. ...
Among various nanotechnology devices, single-electron tunneling devices are the most promising candidates to substitute the present CMOS devices. In this paper, a new single-electron threshold-logic circuit module is presented for realizing and implementing Nano-electronic circuits. The proposed module can be dedicated to implement all basic logic gates, such as OR, NOR, AND, NAND, XOR and XNOR gates, that can be integrated in various manners to design digital circuits. The simulation results demonstrate the accuracy and stability of proposed circuit module. Design capability and flexibility of this module are further evaluated through the synthesis of high-level circuits.
... Figures 8(a) and 8(b) show two familiar architectures to implement°ash-type SET-based ADCs. [24][25][26][27][28][29][30] Data conversion is accomplished by using blocks called as PSF, 31 a symmetric function in the form of F p ðXÞ and a period of T p which satisfy the relation F p ðXÞ ¼ F p ðX þ T p Þ. The output of the PSF depends on the sum of the inputs (X ¼ P x i ). ...
... These blocks are used widely in other SET-based ADC architecture found in the literature. 32 The structure of a hybrid SET/CMOS ADC 26,27,[29][30][31][32] is basically similar to that of Fig. 8(a). Nonetheless, its PSF requires MOS devices in conjunction with metallic SETs. ...
... Currently, all SET-based data converters found in the literature are implemented based on metallic SETs. [24][25][26][27][28][29][30] These architectures are not reliable for room temperature, as stable range of operation for metallic SETs covers only very low temperatures. In general, PSFs are used to perform regular arithmetic operations such as parity checking, adding and subtracting on the digital codes. ...
Room-temperature analog-to-digital converters (ADCs) based on nanoscale silicon (Si) quantum dot (QD)-based single-electron transistors (SETs) can be very attractive for high-speed processors embedded in future generation nanosystems. This paper focuses on the design and modeling of advanced single-electron converters suited for operation at room temperature. In contrast to conventional SETs with metallic QD, the use of sub-10-nm Si QD results in stable operation at room temperature, as the observable Coulomb blockade regime covers effectively the higher temperature range. Si QD-based SETs are also fully compatible with advanced CMOS technology and they can be manufactured using routine nanofabrication steps. At first, we present the principles of operation of Si SETs used for room-temperature operation. Possible flash-type ADC architectures are then investigated and the design considerations of possible Coulomb oscillation regimes are addressed. A modified design procedure is then introduced for (Formula presented.)-bit SET-based ADCs, and validated through simulation of a 3-bit ADC with a sampling frequency of 5 GS/s. The ADC core is comprised from a capacitive signal divider followed by three periodic symmetric functions (PSFs). Simulation results demonstrate the stability of output signals at the room-temperature range.
... Dubuc et al. extended the SET model validity at room temperature up to 430 K. SET circuits are also widely studied for digital and analog applications. Some low complexity structures have been reported [9]- [11]. The impact of circuit parameters of SETs have been also analyzed [12]- [14]. ...
Two compact models for single-electron memory (SEM) are proposed and validated by comparisons with the program SIMON. The approach is based on the master equation method and the orthodox theory. The specific and efficient algorithms for each model are presented. The first model is static and allows directly calculating the final number of electrons on the memory dot. The second model is dynamic, which evaluates every electron tunnel event to assess the stored charge variation and determines the writing or retention times. Both static and dynamic models are written in Verilog-A language and implemented in IC design framework. These SEM models are attractive for circuit simulation to find out the optimal biasing strategy and memory architecture.
... SET is one of single-electron devices researchers most interested in. It is first introduced by Liharev.K.K and up to now, not only its physical properties have been described analytically and calculated approximately, but also the breakthrough in its application has been made [15] [16] [17]. As showed in Fig.1, SET can be simply treated as 3-teminal (gate, source and drain) device, and, there is a so called Coulomb Island between source and drain, where only one or several electrons are permitted to pass over at the same time. ...
In this paper, a new simple hardware-oriented spiking neuron model is proposed. It is mainly based on one of intrinsic features of single- electron transistor (SET)––Coulomb Oscillation. In fact, Coulomb Oscillation can be considered as current pulses under the gate's voltage, which is similar with the pulses of spiking neurons. Accordingly, the circuit structure of spiking neuron model has been designed. By simulation on the PSPICE, the proposed new model can show different spiking types according to the different input signals and implement information encoding. The model can exhibit the property of synchronization. Unlike traditional neuron model, the proposed new model has the capacity of integrating both spatial and temporal signals. In addition the phase encoding is also involved. So the experiments’ results demonstrate that the model is an implement way of hardware-oriented spiking neuron models or even spiking neural networks (SNN).
... The proposed circuits consist of MOS transistors and SET/MOS hybrid circuits. In the SET/MOS hybrid circuits, the SET can be described by a SPICE model [24]- [26]. We used the compact SPICE model to describe the behavior of the SET, whose accuracy has been verified by both MONTE CARLO simulator SIMON [27] and experiments [17]. ...
This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SE s ). The logic gates are based on mosfet based SE turnstiles that can accurately transfer SE s with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the mosfet based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.
... The fundamental principle of SET device action is the coulomb blockade phenomena, which result in on or off states of this transistor [5][6][7] . Some recent applications of SET are switching based such as analog to digital and digital to analog converters [8] and nanometer digital gate design [9] . ...
In this research an emerging field of power electronics in nanotechnology is survived. This application-based technology today is called Nano Power Electronics. It utilizes nano electronic transistors in switching applications in the range of nano power for signal shaping purposes. In recent years Single Electron Transistors are highly interested in nano electronic applications. They have got inherently fast tunneling rate, which makes them highly suitable for high-speed operation. Based on this fact, a novel nano DC/AC converter nano inverter is proposed with these transistors. Simulation of this integrated nano inverter with SPICE shows it has excellent output waveforms and it will be a good candidate for nano power electronic applications.
... The proposed PLL circuit consists of MOS transistors and SEDs. In the SET/MOS hybrid circuits, the SET could be described by a SPICE macro model [15] and a compact SPICE model [16] because the capacitance of the interconnection node between SET and MOS devices is large enough. The accuracy of the compact SPICE model has been verified by both MONTE CARLO simulator SIMON [17] and experiments [6]. ...
This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PLL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PLL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.
