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Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, an...
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... Paralel önek ekleyicileri, ikili toplama problemine yüksek verimli bir çözüm sunar ve FPGA uygulaması için çok uygundur [8]. Mevcut CSLA mimarileri homojen ve heterojen tanımlanmış ve iki yeni hibrit CSLA topolojisi ortaya konmuştur: (i) seçme-alt bölüm-taşıma tabanlı taşıma ileriye dönük toplayıcı taşımak ve (ii) BEC mantığı da dahil olmak üzere seçim bölümü-taşıma tabanlı ileriye dönük toplayıcılar ve çeşitli CSLA yapılarının hız performansları vaka çalışmalarına göre analiz edilmiştir [9]. Han Carlson önek yapısı etkili önek yapısına sahip hibrit modüler paralel önek toplayıcının uygulanması analiz edilmektedir [10]. ...
Gelişen teknoloji çağında modern elektronik sistemlerde daha hızlı uygulamalar daha az enerji tüketimi, alan, güç ve gecikme taleplerini artırmaktadır. Bu araştırma çalışması, paralel toplayıcıların çeşitli sınıflarını ve yapılmış akademik çalışmalardaki hibrit paralel toplayıcıları sunmaktadır. Bu çalışmada önerilen modellerin gecikme, alan, enerji ve güç tüketimi için hibrit paralel toplayıcı performans kriterleri karşılaştırmalı olarak araştırılmıştır. Ayrıca, bu çalışmada araştırılmış olan hibrit paralel toplama araçlarının belirli kriterlere ilişkin performans sonuçları paylaşılmıştır. Elde edilen karşılaştırmalı sonuçlara göre daha az gecikme, alan, güç ve enerji tüketimine sahip hibrit paralel toplayıcı devreleri tasarlanabilecektir. Bu sonuçlara bakılarak çalışma yapılacak alanlar için dizayn yapılacak işlemcilerin toplayıcılar açısından veriler göz önüne alınarak hibrit model seçimleri yapılabilmesi mümkün hale gelecektir. Tablo 1.’de verilen karşılaştırmalı sonuçlar araştırmacılar tarafından deneyler yapılarak elde edilmiş sonuçları göstermektedir. Hibrit paralel toplayıcılar üzerine yapılan bu araştırmada genel olarak tüm uzunluklardaki bitler ele alınmaya çalışılmıştır. Bu paralel toplayıcılar yapılan araştırmalara göre farklı alan, gecikme, güç ve enerji açısından hibrit paralel toplayıcıların deneysel sonuçları bir araya getirilerek karşılaştırmalı analizleri verilmiştir.
... As we know that CLA is the fastest adder, it consists of Generate (G) and Propagate (P) Units, Where Sum and Carry are obtained by Performing Different Operations Using Propagate and Generate Units [7,8,9]. The sum is obtained by Performing Logical XOR Operation using Propagate and Carry Bits. ...
... As discussed discuseed in section I and II i.e., CCLA, SCBCLA, etc., by using conventional architecture [7,8,9]few designs are selected in order to evaluate the behavior of these adders. Fig.4 (a) represents the Hybrid CCLA_1, which means CCLA which is messed with other adders. ...
As the Technology scales, loss of power in devices also goes on increasing, Dynamic loss of power due to switching action of the transistor states, so major challenge or key parameter is the Power, but power parameter should not affect the performance of the Device operation, so this Paper mainly focuses on the software implementation of the Design Targeting the power intent (UPF) and also demonstrates how the UPF models can be used to address the problems faced by the conventional adders in terms of area, power. The power intent is designed at relatively high level of hierarchy which describes which power rails must be routed to the specified block when required and the power is isolated from those unused blocks, as the signal crosses from one power domain to another power domain the power intent also describes the shift in voltage levels.
... Two types of CSLA architectures are common: i) using a RCA in the least significant adder bit positions and using dual RCAs of appropriate size as dictated by the input partitions, one with a fixed carry input of 0 and another with a fixed carry input of 1. The outputs of the dual RCAs are given to 2:1 multiplexers (MUXes) with the carry output of the preceding input partition serving as the select input for the MUXes of the current input partition, and ii) using a RCA for the least significant adder bit positions, and using a RCA of appropriate size as dictated by the input partitions with a fixed carry input of 0 and the outputs of these RCAs are given to a BEC converter [13] which increments the outputs of the RCAs by 1. The selection of either the outputs of the RCAs with a fixed carry input of 0 or the outputs of the BEC converters is done through the MUXes, which have the carry output from a preceding input partition serving as the select input [1,14]. ...
This technical note compares the performance of some synchronous adders which correspond to the following architectures: i) ripple carry adder (RCA), ii) recursive carry lookahead adder (RCLA), iii) hybrid RCLA-RCA with the RCA used in the least significant adder bit positions, iv) block carry lookahead adder (BCLA), v) hybrid BCLA-RCA with the RCA used in the least significant adder bit positions, and vi) non-uniform input partitioned carry select adders (CSLAs) without and with the binary to excess-1 code (BEC) converter. The 32-bit addition was considered as an example operation. The adder architectures mentioned were implemented by targeting a typical case PVT specification (high threshold voltage, supply voltage of 1.05V and operating temperature of 25 degrees Celsius) of the Synopsys 32/28nm CMOS technology. The comparison leads to the following observations: i) the hybrid CCLA-RCA is preferable to the other adders in terms of the speed, the power-delay product, and the energy-delay product, ii) the non-uniform input partitioned CSLA without the BEC converter is preferable to the other adders in terms of the area-delay product, and iii) the RCA incorporating the full adder present in the standard digital cell library is preferable to the other adders in terms of the power-delay-area product.
... However, in comparison with Adder12, Adder15 achieves significant reduction in area by 18.8% while exhibiting a 2.3% increase in the latency. In the future, the utility of the proposed asynchronous RCA involving DBFAs and SBFAs for the effective realization of multi-operand additions [49] based on the bit-partitioning approach described in [50] could be considered since multi-operand addition operations are predominant in digital signal processing applications. Moreover, evaluating the cycle time of the various asynchronous RCAs discussed should be considered since the cycle time determines the rate (speed) at which fresh data can be input to an asynchronous circuit, where the cycle time is the sum of forward and reverse latencies. ...
This technical note presents the design of a new area optimized asynchronous early output dual-bit full adder (DBFA). An asynchronous ripple carry adder (RCA) is constructed based on the new asynchronous DBFAs and existing asynchronous early output single-bit full adders (SBFAs). The asynchronous DBFAs and SBFAs incorporate redundant logic and are encoded using the delay-insensitive dual-rail code (i.e. homogeneous data encoding) and follow a 4-phase return-to-zero handshaking. Compared to the previous asynchronous RCAs involving DBFAs and SBFAs, which are based on homogeneous or heterogeneous delay-insensitive data encodings and which correspond to different timing models, the early output asynchronous RCA incorporating the proposed DBFAs and/or SBFAs is found to result in reduced area for the dual-operand addition operation and feature significantly less latency than the asynchronous RCAs which consist of only SBFAs. The proposed asynchronous DBFA requires 28.6% less silicon than the previously reported asynchronous DBFA. For a 32-bit asynchronous RCA, utilizing 2 stages of SBFAs in the least significant positions and 15 stages of DBFAs in the more significant positions leads to optimization in the latency. The new early output 32-bit asynchronous RCA containing DBFAs and SBFAs reports the following optimizations in design metrics over its counterparts: i) 18.8% reduction in area than a previously reported 32-bit early output asynchronous RCA which also has 15 stages of DBFAs and 2 stages of SBFAs, ii) 29.4% reduction in latency than a 32-bit early output asynchronous RCA containing only SBFAs.
... However, in comparison with Adder12, Adder15 achieves significant reduction in area by 18.8% while exhibiting a 2.3% increase in the latency. In the future, the utility of the proposed asynchronous RCA involving DBFAs and SBFAs for the effective realization of multi-operand additions [49] based on the bit-partitioning approach described in [50] could be considered since multi-operand addition operations are predominant in digital signal processing applications. Moreover, evaluating the cycle time of the various asynchronous RCAs discussed should be considered since the cycle time determines the rate (speed) at which fresh data can be input to an asynchronous circuit, where the cycle time is the sum of forward and reverse latencies. ...
This technical note presents a new area optimized asynchronous early output dual-bit full adder (DBFA). An asynchronous ripple carry adder (RCA) is constructed based on the new asynchronous DBFAs and existing asynchronous early output single-bit full adders (SBFAs). The asynchronous DBFAs and SBFAs incorporate redundant logic and are encoded using the delay-insensitive dual-rail code (i.e. homogeneous data encoding) and follow a 4-phase return-to-zero handshaking. Compared to the previous asynchronous RCAs involving DBFAs and SBFAs, which are based on homogeneous or heterogeneous delay-insensitive data encodings and which correspond to different timing models, the early output asynchronous RCA incorporating the proposed DBFAs and/or SBFAs is found to result in reduced area for the dual-operand addition and pave the way for significantly less latency than the asynchronous RCAs which consist of only SBFAs. The proposed asynchronous DBFA requires 28.6% less silicon than the previously reported asynchronous DBFA. For a 32-bit asynchronous RCA, utilizing 2 stages of SBFAs in the least significant positions and 15 stages of DBFAs in the more significant positions leads to optimization in the latency. The new early output 32-bit asynchronous RCA containing DBFAs and SBFAs reports the following optimizations in design metrics over its counterparts: i) 18.8% reduction in area than a previously reported 32-bit early output asynchronous RCA which also has 15 stages of DBFAs and 2 stages of SBFAs, ii) 29.4% reduction in latency than a 32-bit early output asynchronous RCA containing only SBFAs.
... In literature different architectures of adders namely Ripple Carry Adder (RCA) [2,3], CSA [2,[4][5][6][7][8][9][10][11], CBL [2,7] and SQRT-CSA, Modified SQRT-CSA [6] is available. A brief discussion on above adders is given below for clarity. ...
... Carry select adder (CSLA) is a square root time high-speed adder [1], which offers a good compromise between the low area demand of ripple carry adders (RCAs) and the high-speed performance of carry lookahead adders (CLAs) [2,3]. Both ASIC and FPGA implementations of homogeneous CSLAs, and a hybrid architecture involving CSLA and CLA have been considered in the existing literature based on the synchronous design method [4][5][6][7][8][9][10][11][12][13][14][15][16]. However, with respect to robust asynchronous design methods employing delay-insensitive code(s) for data representation and processing and a 4-phase return-to-zero protocol for handshaking, to the best of our knowledge, there is no dedicated work available in the literature dealing with asynchronous CSLA excepting a theoretical work [17] that proposed just a mathematical model to predict the timing attributes of asynchronous CSLAs. ...
... In some existing literature [25,27,28], ASIC-based asynchronous RCA and CLA implementations corresponding to different timing regimes were considered. In this work, ASIC-based asynchronous CSLA realizations pertaining to two optimum uniform and non-uniform input partitions [16] are considered with respect to a 32-bit dual-operand addition. Fig. 4 shows the CSLA architectures along with the internal details. ...
... The topologies of optimum uniform and non-uniform length CSLAs in the context of a synchronous design are discussed in [16] and the interested reader is referred to the same for details. An example uniform length CSLA with a uniform input partition ...
This paper discusses the standard cell based designs of asynchronous carry select adders (CSLAs) corresponding to strong-indication, weak-indication, and early output timing regimes realized using a delay-insensitive dual-rail code for data representation and processing, and a 4-phase return-to-zero protocol for handshaking. Many 32-bit asynchronous CSLAs corresponding to a uniform input partition viz. 8-8-8-8 and a non-uniform input partition viz. 8-7-6-4-3-2-2 were considered for implementation and comparison. All the asynchronous CSLAs were physically realized in semi-custom ASIC design style using a 32/28nm CMOS process technology. The simulation results show that the 32-bit early output asynchronous CSLA based on the uniform input partition (8-8-8-8) enables optimized data path latency, area occupancy, and average power dissipation compared to the rest.
... 7 and 8 respectively. The best FOM achieved by the hybrid CCLA in the previous work is just 22.5. In contrast, the best FOM achieved by Hybrid CCLA_3 (of this work) is 40.34 as seen in Fig. 7, which signifies a 79.3% increase. ...
The section-carry based carry lookahead adder (SCBCLA) architecture was proposed as an efficient alternative to the conventional carry lookahead adder (CCLA) architecture for the physical implementation of computer arithmetic. In previous related works, self-timed SCBCLA architectures and synchronous SCBCLA architectures were realized using standard cells and FPGAs. In this work, we deal with improved realizations of synchronous SCBCLA architectures designed in a semi-custom fashion using standard cells. The improvement is quantified in terms of a figure of merit (FOM), where the FOM is defined as the inverse product of power, delay and area. Since power, delay and area of digital designs are desirable to be minimized, the FOM is desirable to be maximized. Starting from an efficient conventional carry lookahead generator, we show how an optimized section-carry based carry lookahead generator is realized. In comparison with our recent work dealing with standard cells based implementation of SCBCLAs to perform 32-bit addition of two binary operands, we show in this work that with improved section-carry based carry lookahead generators, the resulting SCBCLAs exhibit significant improvements in FOM. Compared to the earlier optimized hybrid SCBCLA, the proposed optimized hybrid SCBCLA improves the FOM by 88.3%. Even the optimized hybrid CCLA features improvement in FOM by 77.3% over the earlier optimized hybrid CCLA. However, the proposed optimized hybrid SCBCLA is still the winner and has a better FOM than the currently optimized hybrid CCLA by 15.3%. All the CCLAs and SCBCLAs are implemented to realize 32-bit dual-operand binary addition using a 32/28nm CMOS process.
... Ripple carry adders (RCA) [3] are area and power efficient, but with drawback of being slow. Carry-select adders (CSA) [2,[4][5][6][7][8][9][10] are one of the fastest adders among traditional adders, but they are not power and area efficient. Common Boolean Logic (CBL) [7] adders are area-power-delay efficient adders. ...
Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparative analysis of different types of adders in Synopsis Design Compiler using different standard cell libraries at 32/28 nm. Also, the designs are analyzed for the stuck at faults (s-a-0, s-a-1) using Synopsis TetraMAX.
... Also, diverse design styles were considered for the CLA implementation such as self-timed [17] - [19] and synchronous viz. full-custom and semicustom ASIC and FPGA [20] - [22]. Further, as a supplement, various low power design strategies such as multiple supply voltages and/or multiple threshold voltages, adiabatic logic, transistor sizing, and transistor reordering have been considered to effect good optimization of the design parameters viz. ...
The section-carry based carry lookahead adder (SCBCLA) topology was proposed as an improved high-speed alternative to the conventional carry lookahead adder (CCLA) topology in previous works. Self-timed and FPGA-based implementations of SCBCLAs and CCLAs were considered earlier, and it was found that SCBCLAs could help in delay reduction i.e. pave the way for improved speed compared to CCLAs at the expense of some increase in area and/or power parameters. In this work, we consider semi-custom ASIC-based implementations of different variants of SCBCLAs and CCLAs to perform 32-bit dual-operand addition. Based on the simulation results for 32-bit dual-operand addition obtained by targeting a high-end 32/28nm CMOS process, it is found that an optimized SCBCLA architecture reports a 9.8% improvement in figure-of-merit (FOM) compared to an optimized CCLA architecture, where the FOM is defined as the inverse of the product of power, delay, and area. It is generally inferred from the simulations that the SCBCLA architecture could be more beneficial compared to the CCLA architecture in terms of the design metrics whilst benefitting a variety of computer arithmetic operations involving dual-operand and/or multi-operand additions. Also, it is observed that heterogeneous CLA architectures tend to fare well compared to homogeneous CLA architectures, as substantiated by the simulation results.
