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![64-Bit CMOS Binary Comparator [9]](profile/Anjali-Sharma-14/publication/260632302/figure/fig3/AS:342003033362438@1458551285469/64-Bit-CMOS-Binary-Comparator-9.png)
![Fig 4: 2-Bit Comparator using Transmission Gate logic [5]](profile/Anjali-Sharma-14/publication/260632302/figure/fig1/AS:342003033362434@1458551285258/2-Bit-Comparator-using-Transmission-Gate-logic-5_Q320.jpg)
![Fig 5: 2-Bit Comparator using Pass transistor logic style [5]](profile/Anjali-Sharma-14/publication/260632302/figure/fig2/AS:342003033362436@1458551285350/2-Bit-Comparator-using-Pass-transistor-logic-style-5_Q320.jpg)
![Fig 5: 8-Bit Comparator [10]](profile/Anjali-Sharma-14/publication/260632302/figure/fig4/AS:342003033362439@1458551285515/8-Bit-Comparator-10_Q320.jpg)
![Fig 6: CMOS Full Adder Design By 2x1 Mux [11]](profile/Anjali-Sharma-14/publication/260632302/figure/fig5/AS:342003033362440@1458551285582/CMOS-Full-Adder-Design-By-2x1-Mux-11_Q320.jpg)
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Citations
... Hence these estimates create conflict with others. Each individual concern cannot be optimized independently [9]. The GDI and PTL logics were used for One bit hybrid comparator consisting of 17T (8 PMOS and 9 NMOS). ...
Comparator is a basic arithmetic component in a digital system and adders are the basic block of processor unit, the performance of adder will improve the system performance. The proposed 11T adder comparator is consists of three main components, namely XOR, inverter, and MUX logic. The circuit is designed and implemented based on top-down approach with 11 transistors. The proposed cell can be used at higher temperature with minimal power loss. It also gives faster response for the carry output. The proposed comparator circuit shows 63.80% improvement in power consumption than other circuits.
... Among the most commonly used blocks is the one in which there are two AND gates for making outputs A<B and A>B and an OR-NOR gate for forming A=B output. Considering the above mentioned explanations regarding important design parameters such as power and delay, reduction of the number of transistors or area occupation reduction can be considered as the most important and major factors in reducing power and delay [10]. This allows for fewer internal nodes, lower internal capacitors, and less used wire length. ...
In this paper a new magnitude comparator based on transmission gate (TG) technique with 14 transistors is presented. The proposed circuit due to special feature of used technique has low resistivity, internal nodes and internal diffusion and parasitic capacitances. These characteristics drives the circuit with ultra-low power consumption, short paths from inputs to output for achieving high speed rate and finally high PDP dissipation savings. Various simulations using 90nm CMOS technology including VDD, frequency, temperature and load capacitances applied. Also, investigations in term of process corners and possible fabrication process using Monte Carlo performed. Attained results indicated the proposed circuit stability, tolerability, efficiency and low sensitivity to variations under different circumstances such as process voltage temperature (PVT), gate oxide thickness (tox) and diffusion doping concentration (NSD) variations. All attainment suggest the proposed circuit as an appropriate selection for being used in more sophisticated chips for future generation application.
... As magnitude comparator (MC) is very basic arithmetic unit, to cope up with high speed and optimum power for big data analytics, we need suitable MC architecture. Nowadays the implementation and designing of a reversible logic-based magnitude comparator (RMC) with high calculation capacity and low power is very essential for designers [8] . Today's electronics world is competing with ultra-low power and less chip area of digital combinatorial circuits. ...
... As it can be seen, the CNTFET has four terminals like silicon devices. The parts of CNT placed between gate and drain/source are heavily doped to decrease the series resistors of the transistor when the device is on [8] . Also by changing the gate voltage, the device becomes electrically ON and OFF. ...
... Also by changing the gate voltage, the device becomes electrically ON and OFF. The ON current of a CNTFET can be almost given by Eq. (2) , which has a little dependency to the channel length in the case of near ballistic transportation [8] . ...
Reversible or information lossless gates have applications in nano-technology, digital signal processing
(DSP), communication, computer graphics and cryptography. Gate-diffusion input (GDI) technique can
provide the possibility of designing fundamental gates in ultra-low power and layout chip area with low
number of transistors. A reversible logic-based single-bit magnitude comparator (RMC) circuit is pre-
sented by using the modified-GDI (m-GDI) method-based reversible gates for designing RMC in any arbi-
trary number of bit levels for processing at nano-scales.
In this paper, several figure of merits (FOMs) like: energy consumption-propagation delay product
(EDP) and worst delay-power consumption-chip area product (DPA) are evaluated and compared with
other designs. The simulation results show the improvement of the evaluation parameters of the pro-
posed RMC in compare with the other similar basic GDI-based comparators. Also, according to the sim-
ulation results, presented comparator is capable to work at extensive frequency ranges with higher max-
imum operating frequency (fmax.). The effects of different process, voltage and the temperature (PVT)
variations are extensively evaluated by Monte-Carlo simulation. According to the results, the proposed
circuit is robust against PVT variations and also noise-tolerable parameter.
Moreover, the proposed RMC architecture is used in images applications. The results show that output
images of the proposed inexact RMC have a very high quality and resemblance to the images generated
by exact RMC, thus excellent values for the peak signal-to-noise ratio (PSNR) and mean structural sim-
ilarity index metric (MSSIM) indicate that the proposed inexact RMC circuit has a proper accuracy for
applications such as: comparative analysis in medical images, motion detector, edge detection and seg-
mentation in nano-technology. Therefore, using the proposed scheme can be improved in comparator
circuit in chips for future generation of VLSI and ULSI blocks, like: nano-processors performance.
... The inverter used to produce XNOR consumes more area and high power consumption thereby degrading the design performance. (1) CARRY = AB + AC + BC (2) IV. SCHEMATIC DIAGRAM To obtain the three comparative outputs inverted input at the B input terminal is given to the full adder design and C input is connected to the ground. ...
... Power consumption, speed and chip area are the three major estimates in predicting the overall performance of a CMOS comparator design (Etienne and Sonia, 2007b). However, these estimates conflict with one another i.e., each individual estimate can't be optimised independently (Anjali et al., 2013). Hybrid comparator (1-bit) design consisting of 17T by using GDI and PTL logics was introduced. ...
This paper presents an implementation of comparator (1-bit) circuit using a MUX-6T based adder cell. MUX-6T full adder cell is designed with a combination of multiplexing control input and Boolean identities. The proposed comparator design features higher computing speed and lower energy consumption due to the efficient MUX-6T adder cell. The design adopts multiplexing technique with control input to alleviate the threshold voltage loss problem which is commonly encountered in Pass Transistor Logic (PTL) design. The proposed design successfully embeds the buffering circuit in the full adder design which helps the cell to operate at lower supply voltage compared with the other related existing designs. It also enhances the speed of the cascaded operation significantly while maintaining the performance edge in energy consumption. In the proposed design, the transistor count is minimized. For performance comparison, the proposed MUX-6T comparator (1-bit) is compared with four existing full adders based comparators using BSIM4 model parameters. The simulations are performed for 65nm process models indicate that the proposed design has lowest energy consumption along with the performance edge in both speed and energy consumption. The variants namely area and power of the proposed comparator is also compared with the published author designs to validate its suitability for low power and high speed mobile communication applications.
... Any digital circuit with power on whether performing its function or not, consumes power, which is dissipated as heat. Based on the process of power dissipation there are three major sources of power dissipation in CMOS circuits [1] 3. Short circuit dissipationis attributed to short circuit current that arises when pair of NMOS and PMOS transistors conduct simultaneously. ...
... In present day technology scenario due to the increased use of portable electronic devices, power and area efficiency has become a major concern for circuit designers. As direct implementation of area and power efficient technologies on designing platform cannot be cost effective so before actual implementation of these digital circuits on layout it is necessary to take estimation criteria in to consideration on transistor level designing [2]- [3]. So, there is a need of ultra low power designing technology which can reduce the power dissipation as well as area of the VLSI logic circuits. ...
Area efficient ultra low power CMOS digital integrated circuits are one of the emerging technologies for the modern portable systems. Requirement of fewer transistors on chip and less power consumption for the operation of these devices proves the efficiency of these systems. To achieve the efficiency of these devices in terms of area and power, we are on the way to design these devices by using nano technologies. Higher functionally and higher performance of digital circuits at lower power consumption can also be achieved if the required output can be obtained by adding few more transistors in already used circuits in that device. An area-power efficient 42T 4-BitSigned Adder design presented can be tested for functionality using an already designed full adder module. PTL technique based signed adder has been designed on 120nm technology using 21 each of NMOS and PMOS transistors. Three PTL 10-T full adders and one half adder modules has been used in cascade operation to achieve the output of this 4-Bit Signed Adder. Area and power efficiency is achieved in the proposed PTL design as compared to CMOS, TG and GDI technologies. DSCH 3.1 and Microwind 3.1 deigning tool was used to design and simulate the proposed adder circuit on 120nm technologies. Variation in power dissipation with respect to the V DD has been analyzed using BSIM-4 and LEVEL-3 empirical models. The simulation results on 120 nm technology show that the proposed design consumes an area of 630.4 µm2 and a power of 7.877µW at V DD of 1.2V using LEVEL-3 model.
... So the circuit has three outputs to indicate whether A=B, A<B and A>B. So we have the three different outputs equal to logic high according to any given input sequence [7]. ...
... Area, speed and power consumption are the main performance estimation criteria in CMOS Comparator design and these criteria's conflicts with each other i.e. each criteria's can't be achieved simultaneously. In [15] various 1-bit comparator designs have been presented by using 1-bit Full Adder as a basic building block. To achieve output of 1-bit comparator C input of full adder has been connected to the ground and an inverted input has been given at B input terminal. ...
... This 1-Bit CMOS comparator design gives the full voltage swing at the output by disadvantage of this design is the large area consumption as compared to other designs. A TG 36t 1-bit comparator design by using 22T Full Adder has been shown in Fig. 6 [15]. TG based 1-bit comparator designs consume less power and area as compared to complementary CMOS design. ...
... CMOS 1-Bit Comparator Design[15] ...
In this paper an area and power efficient 56T 4-bit comparator design has been presented by using GDI technique. The proposed 4-bit comparator design consist of 28 NMOS and 28 PMOS. A GDI full adder module has been used to design this comparator which consumes less area and power at 120 nm as compared to previous full adder designs. The proposed 4- bit comparator design is based on this area and power efficient 10T full adder module. To get area and power efficiency a centralized full adder module has been used which avoid cascade implementation of XOR module to get sum and carry output. Full adder modules outputs have been used for the generation of output of 4-bit comparator designs. The proposed 4-bit GDI comparator has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. For proposed design Power and current variation with respect to the supply voltage has been performed on BSIM-4 using 120nm technology. Results show that Area of proposed 4- bit comparator design is 1320.3μm2 on 120nm technology. At 1.2V input supply voltage the proposed 4bit GDI comparator consumes 13.739μW power at BSIM-4. At 1.2V proposed GDI 4-bit comparator has shown improvement of 6.3% in terms of area and 69.42% in power as compared to the PTL 4- bit comparator.
... Area, speed and power consumption are the main issues in VLSI design which often conflict with each other and the design methodology and act as constrain on the design of VLSI circuits. These performance criteria's should be individually investigated, analyzed for the various designs of the 1-Bit Subtractor by using different logic styles [3]. Power dissipation in any 1-Bit Subtractor circuit depends on both static and dynamic power dissipation. ...
