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The continuous improving of CMOS technology allows the realization of digital circuits and in particular static random access memories that, compared with previous technologies, contain an impressive number of transistors. The use of new production processes introduces a set of parasitic effects that gain more and more importance with the scaling d...
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... the resulting circuit describes enough of the memory to consider a wide range of faulty behaviors, thus allowing to obtain reasonable results. Figure 1 shows the target memory design while Figure 2 highlights the architecture of a single memory cell realized with a standard 6-transistors structure representing the main objective of our analysis. The list of considered effects is meant to be comprehensive, and it is not related to a specific memory layout. ...
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... list of considered effects is meant to be comprehensive, and it is not related to a specific memory layout. Figure 2 includes a set of eight bridging and coupling ef- fects gaining importance with technology down scaling. They are modeled using eight parasitic capacitors (PC 1 , ..., PC 8 ) considered during the fault analysis. ...
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... defects in the interface between the oxide layer and the substrate of a mosfet transistor may produce an electron trap effect that acts as a capacitance, which can be modeled as an alteration of the capacitive load of the transistor. This effect leads to an alteration of the capacitive load of the CMOS inverter in the self refreshment loop of the memory cell (see Figure 2) identified by PC 1 . The capacitive parasitic effects due to the metallization-substrate coupling and the capacitive coupling between two lines are also additional sources of design variations modeled by PC 2 , PC 3 , PC 4 , PC 5 , PC 6 , PC 7 , and PC 8 . ...
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... PC 6 , PC 7 and PC 8 take into account possible coupling effects between internal cell nodes (i.e., node T or node F of Figure 2), or between internal cell nodes and the corresponding bit line or word line. It is interesting to note that PC 7 leads to a complex dynamic behavior for both technologies, while PC 6 leads to a complex dynamic behavior only for the 65 nm memory. ...
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Citations
... 1475 Table 1 provides specific information on the parasitic capacitors obtained through layout extraction. These capacitors are formed due to the proximity of metal conductors used for signal connections and the placement of transistors [15], [16], [27]. During switching operations, these parasitic capacitors can cause crosstalk noise [28]. ...
... The cap./total value for each signal line of the DLL/DLLB pair indicates the extent of their influence. It is essential to balance these signal lines to prevent interference with the DLL/DLLB [1], [15], [27]. By examining Table 1, it is evident that the signal line with significant capacitance has a notable impact on the total parasitic capacitance, including VDD, VSS, SAEN, and RBL/RBLB. ...
Static random-access memory (SRAM) technology is utilized in designing cache memory to enhance the processing performance of computer systems. The sense amplifier (SA) circuit, a crucial component of memory design, significantly impacts data access time and power consumption. In comparison to conventional differential sense amplifiers (DSA) designs, latch-based sense amplifiers (LSA) used in memory-based computing platforms have specific requirements, including robust noise resistance in harsh working environments and low power consumption, particularly for internet of thing (IoT) embedded computing applications. However, the performance can be degraded due to various factors that arise during the layout, such as conductor resistance or the development of parasitic capacitance. Therefore, this study employs low-voltage 22 nm UMC CMOS technology for LSA design layout and analyzes the factors influencing design performance post-layout process. Layout design optimization techniques are applied to mitigate the impact of parasitic capacitance on important signal lines such as data line/data line bar (DLL/DLLB). Based on the performance analysis results, it is possible to achieve a reduction in power consumption of up to 15% and a 5% decrease in read delay time by implementing circuit layout LSA design optimization techniques.
... Previous works demonstrated through electrical simulations that spot defects may cause misbehavior of a single cell, as well as of multiple cells [8,41,42] . Similarly, parasitic capacitive variations that may arise between adjacent cells, as well as in the single cell, may lead to faulty behaviors [40] . Other works have demonstrated that defects occurring in peripheral memory circuits (e.g., address decoders) can be modeled as equivalent faults in the memory array [43] . ...
Extreme-scale computer systems take advantage of large arrays of general-purpose multi-core processors coupled with specialized manycore accelerators. In order to support complex applications and correctly feed such processing elements, increasingly larger memory cores are integrated at different levels of the hierarchy. However, the adoption of increasingly aggressive manufacturing processes makes the memory subsystem particularly sensitive to faults. Error correcting codes (ECCs) allow the memory to recover from faults at run-time without interfering with the application execution. However, due to the loss of performance introduced every time an error must be corrected, the persistence of faults requires a more radical repair approach in which faulty cells are physically replaced by spare ones. Memory redundancy analysis (MRA) algorithms are used to drive the allocation process of spare resources. Many one-dimensional and two-dimensional MRAs have been proposed, but tools for evaluating their recovering capability are still not well established. This paper presents SIERRA, a simulation environment for precisely evaluating the repair efficiency of an MRA considering different fault signatures and faulty memory configurations. Our simulation engine provides a precise estimation of the MRA quality by analyzing the behavior of the MRA on several faulty memory configurations. To this end, different parameters such as the area of the memory blocks and the defect density are taken into account. The evaluation of the quality of an MRA takes into account its repairing capability, the power consumption derived from its execution, and the area overhead. Thanks to the use of a database for storing information, our tool is able to speed-up the simulation process by distributing it among several nodes. All these features make SIERRA essential in supporting the design of next-generation high-performance computers.
... However, 8T and 10T cells present a high area footprint, limiting the amount of memory that can be included in area-constrained WBSNs. The majority of the silicon real estate of typical WBSN processors is devoted to the memory subsystem, a characteristic that will become even more preeminent in the foreseeable future, as forecasts predict that as much as 95% of the entire chip area will be devoted to memories [27]. Thus, area-hungry 8T or 10T cells should be employed judiciously. ...
This paper introduces an inexact, but ultra-low-power, computing architecture devoted to the embedded analysis of bio-signals. The platform operates at extremely low voltage supply levels to minimize energy consumption. In this scenario, the reliability of SRAM memories cannot be guaranteed when using conventional 6T transistor implementations. While error correction codes and dedicated SRAM implementations can ensure correct operations in this near7threshold regime, they incur in significant area and energy overheads, and should therefore be employed judiciously. Herein, we propose a novel scheme to design inexact computing architectures that selectively protects memory regions based on their significance, i.e., their impact on the end-to-end quality of service, as dictated by the bio-signal application characteristics. We illustrate our scheme on an industrial benchmark application performing the power spectrum analysis (PSA) of electrocardiograms. Experimental evidence showcases that a significance-based memory protection approach leads to a small degradation in the output quality with respect to an exact implementation, while resulting in substantial energy gains, both in the memory and the processing subsystem.
... However, 8T and 10T cells present a high area footprint, limiting the amount of memory that can be included in area-constrained WBSNs. The majority of the silicon real estate of typical WBSN processors is devoted to the memory subsystem, a characteristic that will become even more preeminent in the foreseeable future, as forecasts predict that as much as 95% of the entire chip area will be devoted to memories [16]. Thus, area-hungry 8T or 10T cells should be employed judiciously. ...
Wearable devices performing advanced bio-signal analysis algorithms will foster a revolution in healthcare provision of chronic cardiac diseases. In this context, energy efficiency is of paramount importance, as long-term operations must be performed within an extremely tight power budget. Aggressive voltage scaling is an effective strategy towards this goal, but presents the adverse effect of causing bit-flip errors in the memory sub-system. The application of error correction codes to the whole memory results in large area and energy overheads. To cope with this challenge, in this paper we propose to selectively protect only data presenting high significance, i.e.: highly impacting the end-to-end quality of service. The resulting heterogeneous error protection scheme allows substantial energy savings with respect to complete protection, while resulting in negligible results degradation of cardiac bio-signal processing algorithm
... Accurate estimation of parasitic capacitances is becoming a key step in state-of-the-art post-layout industrial VLSI design flows as it determines the timing, power, and dynamic stability of the integrated circuits (ICs) [1], [2]. These estimated capacitances provide feedback to the designers regarding the final functionality and performance of the design, before silicon integration. ...
With continued scaling of bulk CMOS devices in the nanometer regime, technology computer-aided design (TCAD) assisted extraction of parasitic capacitances has gained importance for predicting the transient behavior of VLSI circuits. In this paper, we present a TCAD structure synthesis and capacitance extraction methodology in a 22nm CMOS process and report parasitic capacitances that affect the oscillation frequency of a 10 GHz voltage-controlled oscillator (VCO). We observe that front-end capacitances are becoming overwhelmingly dominant at nanometer nodes. We quantify the capacitive interactions between the front-end and back-end features using a layer-by-layer capacitance analysis. The estimated frequency tuning range is in agreement with the tuning range of a 22nm VCO hardware.
... However, using all possible CBs while testing for every fault consumes enormous test time, which can be significantly reduced, for the same fault coverage, if only limited required CBs are identified for each functional fault model (FFM). So far, no systematic approach has been proposed that identifies such limited required CBs, nor corresponding optimized memory tests generated that apply limited CBs [1]. Therefore, this paper presents a systematic approach to identify such limited CBs, and thereafter presents an optimized test, March BLC, which detects all static memory faults in the presence of BL coupling using only required CBs. ...
I. INTRODUCTION Memory test optimization can significantly reduce test complexity, while retaining the quality of the test. In the presence of parasitic BL coupling, faults may only be detected by writing all possible coupling backgrounds (CBs) in the neighboring cells of the victim [2], [3]. However, using all possible CBs while testing for every fault consumes enormous test time, which can be significantly reduced, for the same fault coverage, if only limited required CBs are identified for each functional fault model (FFM). So far, no systematic approach has been proposed that identifies such limited required CBs, nor corresponding optimized memory tests generated that apply limited CBs [1]. Therefore, this paper presents a systematic approach to identify such limited CBs, and thereafter presents an optimized test, March BLC, which detects all static memory faults in the presence of BL coupling using only required CBs.
... Research on the impact of parasitic capacitance on the faulty behavior of SRAMs has up till now addressed faults in peripheral memory circuits as well as address decoders [14], [22], [12], [3], [4]. BL twisting as well as BL segmentation (global and local bit lines) have been proposed to prevent cross talk noise and increase the signal-to-noise ratio [7], [8]. ...
The fault coverage of otherwise efficient memory tests can be dramatically reduced due to the influence of bit line coupling. This paper, analyzes the impact of parasitic bit line coupling and neighborhood coupling data backgrounds on the faulty behavior of SRAMs. It investigates and determines the worst case coupling backgrounds required to induce worst case coupling effects, and validates the analysis through defect injection and circuit simulation of all possible spot defects in the SRAM cell array. The paper clearly demonstrates the inadequacies and limitations of several industrial tests in detecting memory faults in the presence of bit line coupling. Finally, it shows how to detect all single-cell and two-cell faults, both in the absence and in the presence of bit line coupling for any possible spot defect.
Technology computer-aided design (TCAD)-assisted automation of structure synthesis followed by a transport-analysis-based capacitance extraction approach has been shown to have a significant potential in the recent past in terms of both accuracy and efficiency. In this brief, we first propose three methods to speedup TCAD-assisted capacitance extraction of an SRAM array layout, by partitioning the layout into several fragments. We demonstrate that the speedup of these partitioning methods, relative to that of TCAD-assisted full-array capacitance extraction method, can be as high as 17x, with an average of 3x. On the other hand, the error in capacitance derived using the partitioning methods can be as low as 1.01%, with an average of 4.93%. We apply the partitioning methods to several layout configurations and styles of FinFET SRAM array layouts and demonstrate their efficacy. We then apply the partitioning methods to a ring oscillator, register, and two-bit adder, and demonstrate similar results.
In this paper, we present a comparative study on the effects of resistive-bridging defects in the SRAM core-cells, considering different technology nodes. In particular, we analyze industrial designs of SRAM core-cell at the following technology nodes: 90nm, 65nm and 40nm. We have performed an extensive number of simulations, varying the resistive value of defects, the power supply voltage, the memory size and the temperature. Experimental results show malfunctions not only within the defective core-cell, but also in other core-cells (defect-free) of the memory array.
