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Citations
... It follows that in subthreshold operation region, the delay increases exponentially with decreasing V DD . Fig. 1 demonstrates the relationship between the supply voltage and the delay of a seven-stage ring oscillator based on an inverter chain in a 65 nm technology node [14]. As can be seen, in subthreshold region delay depends exponentially from V DD , while in superthreshold region the relation is linear. ...
... However, this current is quintessential as far as sub-threshold operation is concerned. Leakage current is utilized by subthreshold circuits as their conduction current [24]. ...
Numerous efforts have made to balance the trade off between power consumption, area and speed of a design. While studying the design at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end and high performance with power within limit at the other has not made. One solution to achieve the ultra-low power consumption is to operate the design in sub threshold region. The use of sub-threshold circuit designing in fast and energy efficient circuits is always needed in electronics industry especially in DSP, image processing and arithmetic units in microprocessors, where the low power is the primary concern and the delay can be tolerated. We design a simple CMOS inverter in weak inversion region (sub-threshold) and compare the power consumption with strong inversion region using Cadence 0.18µm Technology.
The Internet of Things (IoT) paradigm is enabling easy access and interaction with a wide variety of devices, some of them self-powered, equipped with microcontrollers, sensors and sensor networks. Low power and ultra-low-power strategies, as never before, have a huge importance in today’s CMOS integrated circuits, as all portable devices quest for the never-ending battery life, but also with smaller and smaller dimensions every day. The solution is to use clever power management strategies and reduce drastically power consumption in IoT chips. Dynamic Voltage and Frequency Scaling techniques can be rewardingly, and using operation at subthreshold power-supply voltages can effectively achieve significant power savings. However, by reducing the power-supply voltage it imposes the reduction of performance and, consequently, delay increase, which in turn makes the circuit more vulnerable to operational-induced delay-faults and transient-faults. What is the best compromise between power, delay and performance? This paper proposes an automatic methodology and tool to perform power-delay analysis in CMOS gates and circuits, to identify automatically the best compromise between power and delay. By instantiating HSPICE simulator, the proposed tool can automatically perform analysis such as: power-delay product, energy-delay product, power dissipation, or even dynamic and static power dissipations. The optimum operation point in respect to the power-supply voltage is defined, for each circuit or sub-circuit and considering subthreshold operation or not, to the minimum power-supply voltage where the delays do not increase too much and that implements a compromise between delay and power consumption. The algorithm is presented, along with CMOS circuit examples and all the analysis’ results are shown for typical benchmark circuits. Results indicate that subthreshold voltages can be a good compromise in reducing power and increasing delays.
Subthreshold circuits have emerged as a strong alternative for ultralow power applications. This paper first investigates the output levels of the NAND and NOR gates in subthreshold region of operation and carries out analysis on various design metrics. Analysis mainly consists of estimation of propagation delay (tp) and power-delay product (PDP) as a function of supply voltage. It also performs variability analysis of performance metrics such as tp and PDP to determine the robustness of the NAND and NOR circuits in subthreshold regime. Four logic styles were carefully analyzed with a simulation test bench on HSPICE at 16-nm technology. The objective of the analysis is to identify suitable logic family with best performance and least variability with respect to tp and PDP under subthreshold condition, where circuits are susceptible to process, voltage and temperature (PVT) variations. Finally, optimal NAND and NOR circuit was implemented using CNFET technology to achieve even improved results in terms of propagation delay and PDP.
