Fig 8 - uploaded by Akash Levy
Content may be subject to copyright.
4-input 8-bit one-hot multiplexer. Four 8-bit input signals (I í µí± ) are selected by four selection bits (S í µí± ). Only one of the selection bits is hot (S 2 in the example shown).
Source publication
![Fig. 4. Area utilization of the NEM relay in [8] (left) versus this...](profile/Akash-Levy-2/publication/364557676/figure/fig3/AS:11431281092088132@1666704860815/Area-utilization-of-the-NEM-relay-in-8-left-versus-this-work-right_Q320.jpg)
We propose the use of multi-pole nanoelectromechanical (NEM) relays for routing multi-bit signals within a coarse-grained reconfigurable array (CGRA). We describe a CMOS-compatible multi-pole relay design that can be integrated in 3-D and improves area utilization by 40% over a prior design. We then demonstrate a method for placing multiple contact...
Contexts in source publication
Context 1
... an í µí±-input OHMux with NEM relays, we connect í µí± relays by: (1) shorting all of their drains, (2) connecting each source to one of the input signals, and (3) connecting each gate to one of the í µí± selection bits. With multi-pole relays, OHMuxes can multiplex multi-bit inputs. An implementation of an 8-bit-wide 4-input OHmux is shown in Fig. 8. We design 3-D standard cell layouts for {2,4,10}-input 8-bit-wide OHMuxes used in different routing components of the CGRA (discussed in Section 5). The 4-input 8-bit-wide OHMux layout is given in Fig. 9, showing vias routing down to a few CMOS standard cells as an example. Inter-relay signal lines short relays' drains (corresponding ...
Context 2
... top). The end result is that some of the area benefits are lost in practice, as reflected by our ''Area Figure of Merit (FOM)'' metric presented in Section 7.2. Fig. 15(b) illustrates the energy for an input signal (í µí°¼) to propagate to the output (í µí±) through a NEMS/CMOS multiplexer as a function of the capacitive load being driven (see Fig. 8). The largest í µí°¼ → í µí± energy benefit (a 27.5% decrease) is achieved for a 2-input 8b NEMS multiplexer when compared to a 2-input CMOS multiplexer at very small load capacitance (0.21 f F)-a smaller relative benefit is achieved for more inputs and larger load capacitance. Fig. 15(c) illustrates the time required for an input ...
Context 3
... to a 2-input CMOS multiplexer at very small load capacitance (0.21 f F)-a smaller relative benefit is achieved for more inputs and larger load capacitance. Fig. 15(c) illustrates the time required for an input signal (í µí°¼) to propagate to the output (í µí±) through a NEM/CMOS multiplexer as a function of the capacitive load being driven (see Fig. 8). The largest í µí°¼ → í µí± delay benefit (a 4.22× decrease) is achieved for a 10-input 8b NEMS multiplexer when compared to a 10-input CMOS multiplexer at very small load capacitance (0.21 f F)-a smaller relative benefit is achieved for fewer inputs and larger load capacitance. The intuition behind the switching delay improvement is ...
Context 4
... (FEOL) area, and, under the right driver/load conditions, up to 27.5% lower switching energy as well as up to 4.22× lower delay. metric presented in Section 7.2. Fig. 15b illustrates the energy for an input signal (I) to propagate to the 395 output (Z) through a NEMS/CMOS multiplexer as a function of the capacitive load being driven (see Fig. 8). The largest I → Z energy benefit (a 27.5% decrease) is achieved for a 2-input 8b NEMS multiplexer when compared to a 2-input CMOS multiplexer at very small load capacitance (0.21 fF)-a smaller relative benefit is achieved for more inputs and larger load capacitance. to the output (Z) through a NEM/CMOS multiplexer as a function of ...
Context 5
... benefit (a 27.5% decrease) is achieved for a 2-input 8b NEMS multiplexer when compared to a 2-input CMOS multiplexer at very small load capacitance (0.21 fF)-a smaller relative benefit is achieved for more inputs and larger load capacitance. to the output (Z) through a NEM/CMOS multiplexer as a function of the capacitive load being driven (see Fig. 8). The largest I → Z delay benefit (a 4.22× decrease) is achieved for a 10-input 8b NEMS multiplexer when compared 405 to a 10-input CMOS multiplexer at very small load capacitance (0.21 fF)-a smaller relative benefit is achieved for fewer inputs and larger load ...
Citations
... The rest of this chapter is adapted from our published paper [61]. We extend prior work, by ...
... showing that integration of multi-pole NEM relays into a place-and-routed CGRA design improves PPA, thereby reducing reconfigurability overhead [60,61]. The major contributions of this chapter are: ...
In this dissertation, I present techniques for improving the power, performance, and area of integrated circuits (ICs) through 3-D integration of two emerging nanotechnologies: (1) resistive random-access memory (RRAM), a non-volatile memory with multiple-bits-per-cell storage capability, and (2) nanoelectromechanical (NEM) relays, nano-scale mechanical relays that can be actuated electrostatically. In modern ICs for edge computing, data movement between on and off-chip memories typically consumes a large fraction of the total power. Dense, non-volatile embedded memory can reduce/eliminate off-chip data movement by keeping frequently-read application data always on chip. RRAM is a good candidate for such a memory, especially because it can store multiple bits per cell, achieving high density on-chip storage. However, efficient and reliable operation with multiple-bits-per-cell RRAM has been a challenge due to (1) stochastic device behavior during programming that results in large pulse counts with traditional write-verify methods, and (2) reliability issues arising from resistance relaxation. Towards the goal of achieving efficient and reliable multiple-bits-per-cell RRAM, I present three contributions: (1) range-dependent adaptive resistance (RADAR) tuning, a fast and energy-efficient programming method for multiple-bits-per-cell RRAM that uses an adaptive combination of coarse- and fine-grained cell resistance tuning, yielding a 2.4x reduction in pulse count over prior methods, (2) characterization of resistance relaxation behavior in three RRAM technologies and analysis of its implications for multiple-bits-per-cell storage, and (3) efficient multiple-bits-per-cell embedded RRAM (EMBER), the first demonstration of a fully-integrated multiple-bits-per-cell RRAM macro. EMBER contains a multiple-bits-per-cell read and write controller with a high degree of flexibility that enables good level allocation (mitigating reliability issues from resistance relaxation) and programming scheme optimization (yielding low-energy, low-latency multiple-bits-per-cell writes). Finally, in reconfigurable ICs, in addition to the memories, the routing fabric consumes a large fraction of the overall area and power. I demonstrate that replacing CMOS routing switches with 3-D integrated multi-pole nanoelectromechanical (NEM) relays in a coarse-grained reconfigurable array (CGRA) can achieve 19% lower area and 10% lower power at iso-performance.
