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Abstract— In modern VLSI technology, the occurrence of delays has become unavoidable. The data processed by many digital
systems may have delays. Energy efficient design requires understanding of available algorithms, recurrence
structures, energy and wire tradeoffs, circuit design techniques, circuit sizing and system constraints. In this paper,
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Citations
... In Figure[6], it shows the evaluation of an XOR gate using basic gates AndOr and Not gates, which was considered for all the gate calculations. So, a total of 5 gates were required to implement a single XOR gate.Another efficient XOR equivalent circuit is designed and shown in the Figure[7]. The XOR gate is designed with only 4 gates with the help of De Morgan's law.In this proposed design, we replace all the XOR gates in both RCA and AOI with the given circuit. ...
With the revolution in integrated circuits, great emphasis was given on performance and miniaturization. Speed, area and power became the main criterion upon which a VLSI system is measured in terms of its efficiency. In any VLSI system, a full adder is widely component, which decides the performance of the system. The design and analysis of a modified Carry Select Adder(CSLA) is proposed in a cadence 45nm CMOS. It reduces the gate count, thereby area is reduced. Based on modification in CSLA, the process is performed in an efficient way in terms of its gate count and thereby on power and speed.
