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4-bit MDAC implementation used in stage-1, which is identical to Fig. 2(a) except for the addition of a clearing switch (' ) to eliminate the nonlinear charge kickback to V .
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A 16-bit 125 MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.18 ¿m CMOS process is presented in this paper. A SHA-less 4-bit front-end is used to achieve low power and minimize the size of the input sampling capacitance in order to ease drivability. The ADC includes foreground factory digital calibration to correct for capacitor...
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... MDAC implementation used in stage-1 for this design is shown in Fig. 3 along with the timing diagram. This implemen- tation is identical to Fig. 2(a) except that the nonlinear charge kickback problem is solved by using a clearing switch driven by a short pulse [2], [13], [14]. During samples and during connects to REFT or REFB depending on flash data. Before is connected back to , a short clearing pulse ...
Context 2
... to Fig. 2(a) except that the nonlinear charge kickback problem is solved by using a clearing switch driven by a short pulse [2], [13], [14]. During samples and during connects to REFT or REFB depending on flash data. Before is connected back to , a short clearing pulse completely discharges the nonlinear charge . This MDAC implementation shown in Fig. 3 is the key to achieving low power, high SNR and small in this design. ...
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Citations
... Recently, numerous researchers have investigated digital calibration techniques [10][11][12][13][14][15][16][17], since the scaling of CMOS device dimensions offers clear advantages for digital circuitry in terms of area, speed, and integration. According to whether the ADC is calibrated in real time, digital calibration technology is divided into foreground calibration and background calibration. ...
... More specifically, the proposed foreground calibration approach achieves a significant reduction in power consumption by half, while simultaneously attaining a threefold decrease in area, owing to getting rid of the dedicated buffer to generate the calibration voltage. Furthermore, the SFDR of the ADC is comparable to the best results in [10], which is mainly because of the modified MADC and the proposed calibration technique. ...
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... The first stage has a 4-bit resolution and includes a 4-bit sub-ADC [22], a 4-bit sub-DAC, and a residue amplifier, which is shown in Fig.8. The sub-ADC contains sixteen comparators, each producing a thermometer code which is sent to the decoder to generate the control signal for MDAC [23]. ...
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... Since [1] proposed the concept of redundant bits and [2] implemented the 1.5-bit/stage structure, comparator requirements in pipelined analog-to-digital converters (ADC) have significantly relaxed. Since then, pipelined ADC has evolved from just a concept to the preferred structure of high-speed and high-resolution ADC [3,4]. With the rapid development of applications in wireless communication, high-end instrumentation and other fields, there is an increasing demand for higher accuracy of ADC [5][6][7]. ...
As the preferred architecture for high-speed and high-resolution analog-to-digital converters (ADC), the accuracy of pipelined ADC is limited mainly by various errors arising from multiple digital-to-analog converters (MDAC). This paper presents a multi-dimensional (M-D) MDAC calibration based on a genetic algorithm (GA) in a 12-bit 750 MS/s pipelined ADC. The proposed M-D MDAC compensation model enables capacitor mismatch and static interstage gain error (IGE) compensation on the chip and prepares for subsequent background calibration based on a pseudo-random number (PN) injection to achieve accurate compensation for dynamic IGE. An M-D coefficient extraction scheme based on GA is also proposed to extract the required compensation coefficients of the foreground calibration, which avoids falling into local traps through MATLAB. The above calibration scheme has been verified in a prototype 12-bit 750 MS/s pipelined ADC. The measurement results show that the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are increased from 49.9 dB/66.7 dB to 59.6 dB/77.5 dB with the proposed calibration at 25 °C. With the help of background calibration at 85 °C, the SNDR and SFDR are improved by 3.4 dB and 8.8 dB, respectively.
... Therefore, if the calibration accuracy is limited, the small signal conversion is degraded. To improve the linearity of the ADC, the dither technique is usually employed [26][27][28]. It provides several virtual comparison thresholds, which enhance the linearity, especially when the input signal amplitude is small. ...
... We employ the theory in the 16-bit pipelined ADC, in which each stage consists of a flash sub-ADC and an MDAC. As shown in Figure 1, the first two stages resolve more bits than the latter stages owing to a trade-off between the power efficiency and circuit complexity [27]. Capacitor mismatches in the first three stages are calibrated, whereas the capacitor matching accuracy is enough in the back-end stages. ...
... Table 2 illustrates the comparison results with prior works that focused on similar ADC types. Note that only [27] and this work cared about the dynamic performance with a small input signal. Compared to [27], the FoM value in our work was more competitive. ...
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... However, when it comes to multi-bit transmission, such assertion no longer holds. As shown in Figure 9, we conduct an overhead comparison about power consumption and footprint area of DAC/ADC and OE/EO from comprehensive literature reviews [13][14][15][16][17][18][19][20][21]. To guarantee an apple-to-apple comparison, we juxtapose DAC with OE since they both serve as inward-data converter into tiles, and juxtapose ADC with EO because they both serve as outward-data transmitter from tiles. ...
... Thus, the DAC needs to generate multiple references in a single stroke. Even though there are a lot of different types of DACs such as capacitor DAC (CDAC) [19], R-2R based DAC [20], and current-steering DAC [21], they focus on generating a single reference. Therefore, these DAC architectures are not suitable for the multiple reference application. ...
This paper introduces a 12 bit 2.5 bit/cycle SAR-based pipeline ADC employing a self-bias gain boosting amplifier. The single-stage amplifier achieves a low-frequency gain of 37 dB, while consuming 1.3 mW of power consumption with 1.3 V of analog power supply. A 2.5 bit/cycle SAR ADC realizes as the sub-ADC in each stage, and reduces both power consumption and silicon area. A two-channel sampling architecture is employed to double the sampling rate and thereby maximize circuit efficiency. A digital calibration technique is used to reduce non-linearity and mismatches due to the RDAC, as well as gain error and offset of the open-loop residue amplifier. The prototype ADC was fabricated in TSMC 40-nm technology, and consumes 10.71 mW with 1.1 V / 1.3 V digital / analog power supplies. When operating at 125 MS/s, the ADC achieves an SFDR of 66.59 dB before calibration and 80.3 dB after calibration when measured at Nyquist frequency. The experimental results show a Walden FoM of 101 fJ/c.-s. before calibration and 47 fJ/c.-s. after calibration.
... To improve the dynamic performance, the track and hold amplifier(THA) is introduced in [3]. Closed-loop structure has been shown to achieve high linearity up to 16 bits [4], however, it suffers low sampling rate and poor stability due to the existence of the feedback loop. Open-loop structure is widely adopted because of its simple architecture, high speed operation, wide bandwidth [5]. ...
This paper presents a high linearity 4GS/s 4-way time-interleaved track and hold circuit in 65nm CMOS process. A high linearity track and hold amplifier is designed for each single channel, which utilizes open-loop structure instead of traditional closed-loop structure used in low speed applications. In the presented design, we introduced clock-boosting switches and buffers applying source degeneration technique to enable the high linearity. Meanwhile signal feedthrough is cancelled by dummy switches. The proposed design finally achieves over 52 dB signal to noise and distortion ratio (SNDR) for a 400 mV input Vpp at 4GS/s sampling rate.
... Traditionally, residue amplifiers have been implemented by adopting a high-gain amplifier in closed-loop configuration with the gain being set by a capacitive [3], [4] or resistive [7] feedback network. Although capable of achieving excellent gain accuracy, these implementations suffer from large power consumption. ...
... One is the subtractive dither, which must be precisely subtracted from the digital output to minimize SNR degradation. In fact, it sometimes degrades the signal-to-noise and distortion ratio (SINAD) because of the imperfect subtraction of the dither signal [4]. The other one is the nonsubtractive dither. ...
... To take advantage of the redundancy, 16 comparators instead of 14 comparators are employed in the 4-bit per stage architecture [4]. It is worth noting that the two additional comparators are utilized to fold the ends of the transfer function so that at the full-scale input swing, the pipelined stage output is 0 V. ...
In this paper, a new large dither injection technique is proposed for improving linearity in pipelined analog-to-digital converters (ADCs), without losing the dynamic range of the ADCs and deteriorating the corresponding amplifier's linearity. First, analyses of a proper pipelined ADC's architecture are performed for large dither injection. Then, a 9-bit capacitive digital-to-analog converter (DAC) with split architecture is developed to inject the dither ranging from -511/1024 least significant bit (LSB) to 511/1024 LSB of the first stage. To counteract the consumption of the correction range by the capacitive injection dither, the novel 6-bit complementary DACs embedded in the comparator threshold generation circuit are proposed to realize comparator dither injection. In addition, the dither injection amplitude is configurable for investigating different amplitude's effects on the linearity of the ADC. Finally, the proposed dither injection circuit, together with a 16-bit 150 million samples per second (MSPS) ADC, is implemented in a 0.18-μm CMOS technology. The measured results demonstrate the effectiveness of the proposed techniques. The optimum dither is the 9-bit dither, improving not only the spurious free dynamic range (SFDR) of the small signal by at least 13 dB but also that of the large signal by more than 8 dB compared to the case without dither injection. Moreover, dither injection makes the noise floor clean.
... The digital pseudo-random (PN) calibration algorithm used for the main pipeline stages is used to minimize the non-ideal errors and improve the dynamic performance [5][6][7][8]. The accuracy of switched-capacitor circuits in pipeline ADC is limited mainly by finite operational amplifier (op-amp) gain, capacitor mismatch and settling error. ...
... The MDAC used in this 4.5-bit sub-stage circuit is implemented by traditional switched capacitor MDAC scheme, which consumes major current to achieve accurate gain and high bandwidth. The Fig. 2 [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] is same with right control signal. The PN noise is injected in the voltage references by randomly varying the comparator threshold level, which is realized by randomly selecting the reference control switches PN 1 to PN 16 . ...
A 12bit 250MSPS pipeline analog-to-digital converter (ADC) with serial output interface is presented. The pseudo random digital calibration dithered sub-ADC in first stage is used to lower non-ideal errors and improve the dynamic performance in the high speed ADC. An integrated serial output interface is implemented to convert 12bit parallel data into a differential serial data stream. The pipeline ADC was fabricated with CMOS 180 nm 1.8 V 1P5 M process. The active ADC with the serial output interface consumes a power consumption of 395 mW and occupies an area of 8.0 mm², where the active area of the interface is 0.75 mm². The measurement results show that the differential non-linearity and integral non-linearity of the proposed ADC are − 0.22/+ 0.16LSB and − 0.4/+ 0.6LSB, respectively. The spurious free dynamic range and signal-to-noise ratio can get 81.17 dB and 69.92 dB with 20 MHz input signal at full sampling speed. The serial output interface provides an eye height greater than 800 mV for data rates of 4 GHz bits per second with a power of 75 mW.
... Considering a thermometer MDAC with one switched-capacitor branch per comparator, 27 the calibration logic can be placed as shown in Figure 6 out of the critical time-constrain signal path, since this MDAC architecture is immune to transitions inversions. This approach provides a complete clock cycle for settling, relaxing its design. ...
This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15‐bit resolution (74 dB‐Signal‐to‐noise plus Distortion Ratio [SNDR]). A self‐repairing (SR) thermometer‐to‐binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one‐half least‐significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15‐bit pipeline ADC using a novel calibrated dynamic‐latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications. This paper presents a fast background calibration method for comparator offsets in pipeline ADCs. A self‐repairing (SR) thermometer‐to‐binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one‐half least‐significant bit (LSB). Its application to a 1.8 V 0.18 μm 15‐bit 100Msps pipeline ADC using a novel calibrated dynamic‐latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration.
