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As more and more confidential information is being transmitted securely, the use of cryptographic algorithms is expanded. However, existing cryptographic algorithms are subject to various malicious attacks. Fault injection attack is one of the most effective attacks that are able to extract private information with the inexpensive requirement and s...
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Full text available here: http://ietdl.org/t/r8xiRb
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Citations
... It should be noted that the injected errors cause erroneous AES results which make the encrypted message output unreliable. To improve the robustness of the AES implementation, until to date, a few fault detection schemes have been proposed [9][10][11][12][13][14][15][16][17]. ...
... Sheikhpour et al. [11] proposed a three fault-tolerant architectures which provide different security levels of fault tolerance for AES 128-bit. Those architectures can tolerate all permanent and transient faults. ...
... Tab. 6 compares the proposed architecture with 5 similar reported works [9][10][11][12][13] in terms of fault coverage (FC), area, frequency, throughput and efficiency overheads. It should be noted that since most similar works classify the faulty outputs as undetected error and detected error, we considered the silent fault and false positive as detected error. ...
The Advanced Encryption Standard cryptographic algorithm, named AES, is implemented in cryptographic circuits to ensure high security level to any system which required confidentiality and secure information exchange. One of the most effective physical attacks against the hardware implementation of AES is fault attacks which can extract secret data. Until now, a several AES fault detection schemes against fault injection attacks have been proposed. In this paper, so as to ensure a high level of security against fault injection attacks, a new efficient fault detection scheme based on the AES architecture modification has been proposed. For this reason, the AES 32-bit round is divided into two half rounds and input and pipeline registers are implemented between them. The proposed scheme is independent of the procedure the AES is implemented. Thus, it can be implemented to secure the pipeline and iterative architectures. To evaluate the robustness of the proposed fault detection scheme against fault injection attacks, we conduct a transient and permanent fault attacks and then we determine the fault detection capability; it is about 99.88585% and 99.9069% for transient and permanent faults respectively. We have modeled the AES fault detection scheme using VHDL hardware language and through hardware FPGA implementation. The FPGA results demonstrate that our scheme can efficiently protect the AES hardware implementation against fault attacks. It can be simply implemented with low complexity. In addition, the FPGA implementation performances prove the low area overhead and the high efficiency and working frequency for the proposed AES detection scheme.
... This technique is not able to detect permanent faults. A High throughput fault-resilient architecture for 128-bit AES (HFA) is introduced in [22]. The HFA is constructed of four equivalent blocks and each of them is divided into two pipeline stages. ...
... Some of the selected architectures in this set have been developed with the aim of achieving a high level of reliability in a small area (i.e. most of the 128-bit architectures), similar to our aims [20,22,27]. Table 1 lists the evaluation and comparison design features for some of the similar 8-, 32-and 128-bit AES implementations. ...
... In fact, these two techniques are the most popular fault-tolerant techniques for the error correction task. The fault-resilient architectures in [20,22,27] fall in the category of 128-bit AES architectures and so suggest higher throughput as compared to any introduced 32-bit architecture. Our architectures have a much smaller implementation area but less frequency and throughput than [22]. ...
Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low-cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the reliability of our AES architecture, the reliability of voter is very important, for which reason we have introduced a novel voting scheme include a majority voter (named TMR voter) and an error barrier element (named DMR voter). In this paper, a reliable and secure 32-bit data-path AES implementation based on our robust fault resilient approach is developed. We illustrate that the proposed architecture can tolerate up to triple-bit (byte) simultaneous faults at each pipeline stage’s logic and verify our claim through extensive error simulations. Error simulation results also show that our architecture achieves close to 100% fault-masking capability for multiple-bit (byte) faults. Finally, it is shown that the Application-Specific Integrated Circuit implementation of the fault-tolerant architectures using the composite field-based S-box, CFB-AES, and ROM-based S-box, RB-AES allows better area usage, throughput and fault resilience trade-off compared to their counterparts. So, it provides the most appropriate features to be used in highly-secure resource-constraint applications
The Internet of Things (IoT) as an emerging infrastructure has an essential rule in daily lives in many domains, ranging from healthcare wearable devices to complex industrial systems. Nevertheless, its security is a challenging issue that has to be addressed. The security can be settled by utilizing cryptographic techniques such as Advanced Encryption Standard (AES) for encryption and authentication. In this paper, we propose 32-bit architecture AES encryption/decryption for utilizing in IoT infrastructure and similar resource-constrained applications. On the other hand, providing robustness against existing malicious attacks is a significant factor in ensuring communication reliably and so securely. Therefore, we propose a low-cost fault-resilient integrated architecture, named LC-FRAES, for data-path and also on-the-fly key expansion unit by exploiting of resource sharing between encryption and decryption processes. The results of both ASIC and FPGA implementations of the proposed architecture are reported and also compared with those of similar recent designs. The comparisons illustrate that the LC-FRAES outperforms its counterparts in many architectural features which make it suitable for IoT applications. Moreover, we provide a comparison between our proposal and lightweight cryptographic designs from literature. The comparisons verify the consistency and appropriateness of proposed architecture for IoT applications. Finally, through the extensive experimental results, we show that LC-FRAES can detect almost all injected faults.
