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The multi-core processor of RISC for network packet forwarding has been limited by the on-chip storage space. As more and more cores are implemented in one chip, the storage resources allocated by each core on the chip become less and less, as well as the conflict of visiting RAM has become more prominent. Therefore, the use of more compact instruc...
Citations
... [31] reports similar code size for RV32EC and ARM Thumb-2 when considering the SPEC CPU2006 benchmark suite. As the frequency of instructions and the number of registers employed varies with the application, [32] defines a non-standard extension to reduce code size for a specific application. ...
This paper proposes a roadmap to address present and future needs in space systems with RISC-V processors. RISC-V is an open and modular Instruction Set Architecture (ISA) which is rapidly growing in popularity in terrestrial applications. In order to satisfy different applications with contrasting requirements in satellite data systems, four different types of processors are identified: 1) low-area/low-power microcontrollers,
2) On-Board Computers (OBCs), 3) general-purpose processors for payloads and 4) enhanced payload processors for Artificial Intelligence (AI). Several solutions based on RISC-V are proposed for each of these types of processors and compared to proprietary Commercial-Off-The-Shelf (COTS) and space-grade solutions. An extensive analysis of the results available from literature is conducted to show that RISC-V has
the potential to solve such a wide range of needs. We will also show the unprecedented number of open-source implementations and models that were developed in a relative short time on a single ISA. Future space systems could benefit from many of those developments and in this work we identify and highlight what is still missing to satisfy the specific needs of processors for space, especially in terms of fault tolerance and Technology Readiness Level (TRL).
In embedded graphics systems, the graphics processing unit (GPU) also consumes significant amount of frame buffer memory bandwidth. Frame buffer compression is widely adopted to alleviate both memory bandwidth and power consumption issues for the display controller, but rarely has it been applied to addressing GPU’s consumption. This paper proposes a real-time fixed-ratio frame buffer compression technique for RISC-V processor-based embedded graphics systems. The advantage of the proposed method is that the fixed-ratio compressed frame buffer can be directly adopted as an input texture by GPU. The proposed architecture (called an FBC coprocessor) is a hardware extension to the RISC-V microprocessor that supports frame buffer memory bandwidth reduction. The results show that the coprocessor consumes only 1% additional silicon space of the whole system, while reducing bandwidth consumption by 72.64%. A prototype system-on-a-chip indicates that the proposed FBC coprocessor can reduce GPU power consumption by up to 12.7% for an example automotive application.
