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With technology scaling down to 90nm and below, many yield-driven design and optimization methodologies have been proposed to cope with the prominent process variation and to increase the yield. A critical issue that affects the efficiency of those methods is to estimate the yield when given design parameters under variations. Existing methods eith...
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... However, MC typically requires millions, or even billions of samples to reach reasonable accuracy, which is prohibitively costly. Therefore, other approaches based on importance sampling (IS) [2] and boundary-searching [3] are developed. The basic idea of IS is to sample the failure regions with distorted probability density function. ...
In advanced manufacturing technology, SRAM yield estimation with correlation is a significant challenge due to process variations and structures especially at low voltage. In this paper, Double Asymptotic Probability Approximation (DAPA) method with Subset Analytical Model (SAM) is proposed to effectively estimate the probability of correlated failure event. SAM models SRAM failure events based on simulation of subsets of the equivalent circuit. DAPA obtains the recursive function of partial failure rate. The key idea is to approximate the failure rate of the entire system based on a linear combination of partial failure rates by decoupling failure correlation. Under TSMC 28 nm process, ( M = N = 8 ) SRAM failure rate is estimated at 500 mV with an error of less than 5% by the proposed method. Besides 2.5 hours of modeling consumption, the calculation can be completed in 7 seconds, which greatly reduces SRAM failure estimation time, compared with Monte Carlo method.
... To mitigate the inefficiency issue of MC method, various methodologies have been proposed in the past decade including advanced sampling techniques [7] [8] and boundary searching methods [9]. However, most of the existing approaches are either not general enough [8] or can be successfully applied to problems with a small number of process parameters, but, perform poorly with high-dimensional problems [9]. ...
... To mitigate the inefficiency issue of MC method, various methodologies have been proposed in the past decade including advanced sampling techniques [7] [8] and boundary searching methods [9]. However, most of the existing approaches are either not general enough [8] or can be successfully applied to problems with a small number of process parameters, but, perform poorly with high-dimensional problems [9]. Given such limitations, a yield analysis method that tries to address the shortcoming of the above approaches is highly demanded. ...
... Other existing methods try to construct a surface boundary which separates the success and failure regions [9]. Once the boundary is constructed, the yield can be obtained by computing the volume of the failure region without circuit simulation. ...
Existing yield analysis methods are computationally expensive and generally encounter challenges with highdimensional process parameters space. In this paper, we propose a new method for accelerated and reliable computation of parametric yield that combines the advantages of sparse regression and Satisfiability Modulo Theory (SMT) solving techniques, and avoids issues in both. The key idea is to characterize the failure regions as a collection of hyperrectangles in the parameters space. Towards this goal, the method constructs a sparse polynomial models based on adaptive LASSO (Least Absolute Shrinkage and Selection Operator) to find a low degree approximations of the circuit performances. A procedure inspired by statistical model checking is then introduced to assess the model accuracy. Given the constructed models, an SMT-based solving algorithm is employed to locate the failure hyperrectangles in the parameters space. The yield estimation is based on a geometric calculation of probabilistic volumes subtended by the located hyperrectangles. We demonstrate the effectiveness of our method using circuits that require expensive run-time simulation during yield evaluation. They include: an integrated ring oscillator, a 6T static RAM cell and a multi-stage fully-differential amplifier. Experimental results show that the proposed method is suitable for handling problems with tens of process parameters. Meanwhile, it can provide 5X2000X speed-up over Monte Carlo methods, when a high prediction accuracy is required.
... Meanwhile, a large number of parameter-domain methodologies have been developed as well: nonlinear surface sampling [7] locates the points on the " yield boundary " by searching along the nonlinear performance surface in the parameter domain. Global search method [8] can find one point on the " yield boundary " with one-time simulation and thus save more runtime. Response surface modeling method [9] tries to model the performance as a polynomial function of all variable parameters and then evaluate the yield estimation. ...
... Quasi Monte Carlo [1][2], Importance Sampling[4][5][6]) in the performance domain, and two recent-established methods in the parameter domain (e.g. nonlinear surface sampling method [7] and global search method [8]). We have compared all these approaches quantitatively by several circuit examples from the perspectives of both accuracy and efficiency. ...
... Therefore, the parametric yield estimation methods in the parameter domain aim to locate points on the hyper-surface boundary (or called " yield boundary " ) efficiently and accurately. In this section, we will present two yield estimation approaches (i.e., Nonlinear Surface Sampling [7] and QuickYield [8] in the parameter domain, which can efficiently estimate the yield with very high accuracy along with hundreds times speedup over Monte-Carlo. Also, we use a ring-oscillator as an example to compare these methods and the reasons are two-fold: 1) QuickYield [8] can only be applied to DC and PSS (periodical steady state) analyses and the evaluation of oscillator period needs PSS analysis. ...
The undesired uncertainties in circuit performance can lead to analog/mixed-signal circuit failures and yield loss at nanoscale. As such, it has become extremely critical for high precision analog/RF circuits such as phase-locked loop (PLL) and custom/mixed-signal circuits such as SRAM arrays, which both have tight operating margin due to lower power supply and higher operating frequency. Many performance-domain techniques have become available in past few decades: the Monte Carlo (MC) method repeatedly draws samples, runs simulations, and evaluates the yield rate, which can be easily applied to high-dimensional problems. However, it is extremely time consuming. IS can reduce the number of samples required to achieve a desired accuracy, especially in the case where the failure region is small for rare failure events. However, it is always challenging to obtain an optimal sampling distribution or shift vector efficiently.
... Large-scale process variations have become inevitable in the nano-technology era [1], [2] and significantly change the behavior of analog/mixed-signal (AMS) circuits (e.g. voltage swing, timing delay, clock frequency, etc.) [3], [4], [5], [6], [7], [8], [9]. Therefore, it is urgently sought to accurately extract the probabilistic behavioral distribution of AMS circuits under process variations. ...
It has become increasingly challenging to model the stochastic behavior of analog/mixed-signal (AMS) circuits under large-scale process variations. In this paper, a novel moment-matching based method has been proposed to accurately extract the probabilistic behavioral distributions of AMS circuits. This method first utilizes Latin Hypercube Sampling (LHS) coupling with a correlation control technique to generate a few samples (e.g., sample-size is in linear with number of variable parameters) and further analytically evaluate the high-order moments of the circuit behavior with high accuracy. In this way, the “arbitrary” probabilistic distributions of the circuit behavior can be extracted using moment-matching method. More importantly, the proposed method has been successfully applied to high-dimensional prob-lems with linear complexity. The experiments demonstrate that the proposed method can provide up to 1666X speedup over crude Monte Carlo method for the same accuracy.
... A robust design beyond 90nm is challenging due to process variations [Cox et al. 1985;Pelgrom et al. 1989;Lampaert et al. 1995;McAndrew et al. 1997;Schenkel et al. 2001;Drennan and McAndrew 2003;Biagetti et al. 2004;Vrudhula et al. 2006;Kim et al. 2007;Pileggi et al. 2008;Nassif and Nowka 2010;Liu et al. 2010;Gong et al. 2011;Wang et al. 2009;Gong et al. 2010;Gong et al. 2009]. The sources of variation can come from etching, lithography, polishing, and stress, etc. ...
Yield failure has become an emerging issue for both digital and analog designs beyond 90nm. The inevitable physical-level process variations can significantly affect system-level performance such as reliability and robustness. One fast estimation for yield with further optimization has become highly desirable for both process and circuit designers. In this paper, a fast non-Monte-Carlo (NMC) method is developed to capture physical-level stochastic variations for system-level yield estimation and optimization. Based on the newly developed stochastic or-thogonal polynomial (SOP) expansion, an efficient and true NMC mismatch analysis is developed to estimate the parametric yield. Moreover, this work is the first in literature to further derive the stochastic sensitivity for yield within the framework of SOP. Using sensitivities, a corresponding multi-objective optimization is developed to improve the yield-rate and other performance merits, simultaneously. As a result, our proposed approach can automatically tune design parameters for a robust design. Extensive experiments show that when compared to the Monte-Carlo-styled yield estimation, our NMC mismatch method can achieve up to 700X speedup and maintain 2% accuracy. Also, multi-objective op-timization can improve yield-rate up to 95.3% and enhance other performance merits when compared to other existing methods.
As high-density SRAMs must be designed to ensure a substantially small failure rate, the accurate yield estimation with practically acceptable runtime of circuit simulations is highly challenging. Here, a read access yield estimation method for high-density static random access memory (SRAM) is proposed. Instead of performing SPICE runs for the entire SRAM circuit, the proposed method partitions the SRAM into three parts—the control signal generation circuit, bitcell array, and sense amplifier (SA)—that determine three key parameters: word-line to SA enable delay, bit-line voltage difference, and SA offset voltage. Subsequently, the proposed method derives the probability density of these key parameters from each of the three partitioned circuits. Here, different methods are applied to derive the probability of the key parameters, considering the respective characteristics of each circuit part and parameter. According to our experimental results, the proposed method can accelerate the yield estimation by 500–3000×, compared with the brute-force Monte Carlo simulation method, and 10–100× compared with the other state-of-art methods. In addition, the proposed method can accelerate the circuit optimization procedure accompanied by multiple circuit revisions, that is, the circuit revisions can be reflected with SPICE runs only for the revised circuit part, unlike the previous methods that require SPICE runs for the entire SRAM.
Parametric yield is a significant threat to the reliability of nanoscale Analog and Mixed-Signal (AMS) circuits. A critical yet challenging problem of yield estimation is to account for multiple circuit performance. In this paper, we propose a novel nonparametric statistical verification methodology to efficiently estimate the parametric yield due to 65nm technology for multi-performance constraints. Our proposed approach exploits the fact that circuit parameters variation has different impacts on the circuit performance. Hence, a global sensitivity analysis classifies the circuit parameters according to their influence on the desired circuit performances. Based on this classification, an efficient Joint Recurrence Verification (JRV) algorithm, a procedure inspired from DNA analysis, is performed on the most “critical/influential” parameters. A global hypothesis testing procedure is then performed based on the computed JRV metrics. We demonstrate the effectiveness of our methodology on two benchmark circuits. The acquired results show the ability of our approach to handle multiple corners and multiple performances yield problems with up to 11X speedup compared to conventional techniques with an average error smaller than 3%.
Yield¹ analysis of SRAM is a challenging issue, because the failure rates of SRAM cells are extremely small. In this article, an efficient non-Gaussian sampling method of cross entropy optimization is proposed for estimating the high sigma SRAM yield. Instead of sampling with the Gaussian distribution in existing methods, a non-Gaussian distribution, i.e., a joint one-dimensional generalized Pareto distribution and (n-1)-dimensional Gaussian distribution, is taken as the function family of practical distribution, which is proved to be more suitable to fit the ideal distribution in the view of extreme failure event. To minimize the cross entropy between practical and ideal distributions, a sequential quadratic programing solver with multiple starting points strategy is applied for calculating the optimal parameters of practical distributions. Experimental results show that the proposed non-Gaussian sampling is a 2.2--4.1× speedup over the Gaussian sampling, on the whole, it is about a 1.6--2.3× speedup over state-of-the-art methods with low- and high-dimensional cases without loss of accuracy
