Fig 3 - uploaded by Shaowu Huang
Content may be subject to copyright.
3-D models used in HFSS simulations for characterizing coupled stripline differential pair.
Source publication
In this paper we present an approach to improve the accuracy of mixed-mode S-parameters including differential insertion loss calculations using the single-ended simulation or/and measurement results for transmission lines. A correction term is derived to improve the conversion from 4-ports single-ended S-parameters to differential insertion loss....
Context in source publication
Context 1
... this section, we use 3D full wave simulator HFSS to solve the S-parameters for two differential microstrip pairs, as showed in Fig. 1. Fig. 1 (a) is an uncoupled microstrip pair, with the trace separation distance = 75mils = 12.5 ൈ the trace width. Fig. 1 (b) is a coupled microstrip pair, with the trace separation distance = 5.5mils = 0.92 ൈ the trace width. Other geometry and material parameters are same for both cases as in Table I. shows the simulation setup for geometry and dielectric. HFSS simulation results are showed in Fig. 2. Fig. 2. (a) is for uncoupled microstrips. The result of traditional formula (10), ܵ ଶଵ ൌ ͲǤͷ ή ሺܵ ௌாଶଵ െ ܵ ௌாଶଷ െ ܵ ௌாସଵ ܵ ௌாସଷ ሻ , agrees with that of the new formula (15), ܵ ଶଵ ௪ ൌ ሺଵା ವ ሻାሺଵି ሺଵା ವ כ ವ ሻ ሻௌ ವವభభ ܵ ଶଵ . This means the coupling is very small, so traditional formula works well. Fig. 2. (b) is for the coupled microstrips. Clearly, traditional formula does not agree with new formula, due to the coupling between two traces. This indicates the new formula is needed for the better accuracy. In Table II compares the results at 4GHz and 8GHz. We see the difference is 0.06 dB per inch at 8GHz for a 4 inch coupled microstrip routing. In this section, demonstrate the new equations can be used to de-embed the multiple reflections, so that different coupon lengths will give same results. Thus, the coupon length can be significantly reduced. We use 3D full wave simulator HFSS to solve the S- parameters for a differential stripline pair, as showed in Fig. 3. Fix different coupon lengths are used for comparison: 0.5 inch, 1 inch, 2 inches, 4 inches, and 8 inches. The results are showed in Fig. 4. In Fig. 4 (a), the different coupon lengths give different insertion loss numbers by using traditional formula (10). The 8 inches have the best accuracy, since the same amount of error is scaled into per inch (divided by 8 for using 8 inches, and divided by 0.5 for using 0.5 inch). In Fig. 4(b), different coupon lengths give the same results by using new formula (15). And the result very close to the 8 inches results in Fig. 4 (a). This indicates, using new formula (15), the coupon length can be reduced to much smaller than the length of 8 inches, which is required in industry conventional ...
Citations
... BIST is a mode of operation of a chip other than its normal mode, where when a chip is switched to this mode, it performs its test by itself. Nowadays mixed-mode testing approach [31][32][33][34][35] is the state of the art technique for BIST implementation where the ASIC is tested using both pseudo-random test patterns for easy to test faults and deterministic test patterns for hard to detect faults, and thereby, maximum fault coverage is achieved. In this research, the mixed-mode BIST technique has been incorporated into the design of the AES cryptoprocessor ASIC. ...
... Initially, the same deterministic approach as used in ATE was used in BIST. However, later on, a number of techniques have been proposed to improve the performance of the BIST such as pseudo-random testing approach [39] weighted random testing approach [40,41], mixed-mode testing approach [31][32][33] etc. Later on, different variants of mixed-mode testing approaches are proposed [34,35]. ...
This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.
... There are many methodologies which have been developed. There are techniques proposed to reduce the coupon length and improve the accuracy of PCB Tline characterization [5][6][7], which are critical for high volume manufacturing environment because of the cost concern. Recently the Delta-L method, which uses vector network analyzer (VNA) to capture the S-parameters then do post-process similar to SPP, is proposed. ...
In this paper, a new de-embedding technique with Look-Up Table (LUT) is proposed for accurate and efficient characterization of interconnects, particularly printed circuit board (PCB) transmission lines including microstrip and stripline. LUT is pre-created to cover various fixture effects including the reference structures inside and/or outside test printed circuit boards (PCBs). The pre-established LUT is introduced to eliminate the errors of "probing and launching fixtures" in characterization of transmission lines. It is applied to characterization of loss of microstrip and stripline. Simulations and measurements are performed to verify its accuracy and feasibility. Results show it is in good agreement with conventional Delta-L like methods but significantly reduces the cost of characterization. It provides an accurate but cost-effective solution for characterization of high speed interconnects, in particular for high volume manufacturing environments.
High-speed transmission lines are commonly routed as differential lines to control sensitivity to noise on the reference planes at higher speeds. Differential lines are typically characterized in terms of mixed-mode scattering parameters, as they provide insight into the behavior of differential and common signals, as well as the mode conversion among them. These mixed-mode scattering parameters can be mathematically obtained from single-ended parameters, which can, for example, be measured with a four-port vector network analyzer. There has been recent efforts to develop extended or modified versions of mixed-mode scattering parameters, especially for tightly-coupled lines. This can be a point of confusion in interpreting the behavior of differential lines. In this paper, we introduce the mixed-port scattering and hybrid parameters, which do not suffer from any such ambiguous definitions. Mixed-port hybrid parameters are the most natural way to represent any four-port differential circuit, as they are based on intuitive differential and common-port excitations of the network. They also enable extraction of the current division factor experimentally, which is a critical parameter for electromagnetic interference analysis of differential lines. Mixed-port scattering parameters are also defined based on common and differential port excitations, allowing a simpler interpretation than their mixed-mode counterparts, without the need for defining even, odd, common, or differential-mode impedances. As such, mixed-port scattering and hybrid parameters can be used to analyze the performance of a general differential network, certainly including coupled or asymmetrical lines, without any ambiguity.
In this paper, we present a new formulation for the conversion of mixed-mode S-parameters from single-ended S-parameter results. The formulation can be used to improve the accuracy of the characterization of mixed-mode S-parameters including the measurement of differential insertion loss S-parameters (SDD21) for transmission lines. The formulation can also be used to reduce the length of test structures or coupons with an acceptable rate of accuracy. The formulation is an explicit expression, which is also useful as a basis for other derivations and applications. For example, the single-ended transmission to differential insertion loss (SET2DIL) formula can be simply derived from the SDD21 term. The applications to coupled microstrips and striplines are illustrated. The method is compared to time-domain methods for SDD21 characterization. Simulation and measurement results are shown to validate the method.
This paper proposes novel mixed-mode S-parameters, which are dubbed as “extended mixed-mode S-parameters.” The extended mixed-mode S-parameters were applied to three-conductor transmission lines, resulting in the independent differential and common modes using the current division factor of three-conductor transmission lines. By contrast to the conventional mixed-mode S-parameters, there are no cross-mode S-parameters in the extended mixed-mode S-parameters, even in the asymmetrical conductor transmission lines. In addition, two new mode conversion matrices, which contain the current division factor, are also proposed to convert the extended mixed-mode S-parameters to the standard S-parameters. The validity of the proposed extended mixed-mode S-parameters and the mode conversion method were confirmed by comparing the S-parameters from the theory, EM-simulation, and experiment as well.
