FIGURE 2 - uploaded by Kaustav Banerjee
Content may be subject to copyright.
2D materials offer a wide range of electronic properties, including insulator, semiconductor, and metal, in multiple families, as illustrated at the four corners. The inset schematic at the center shows two vertically stacked 2D FETs with h-BN as the ILD material.
Source publication
As a possible pathway to continue Moore’s law indefinitely into the future as well as unprecedented beyond-Moore heterogeneous integration, we examine the prospects of building monolithic three-dimensional integrated circuits (M3DIC) with atomically-thin or two-dimensional (2D) van der Waals materials in terms of overcoming the major drawbacks of c...
Contexts in source publication
Context 1
... dimensional (2D) van der Waals materials (Fig. 2), including graphene, and beyond-graphene 2D crystals (e.g., MoS 2 and WSe 2 ) [12] have recently shown great potential for next-generation electronics because of their unique 2D nature and ultimately thin bodies [13], [14]. The concept of building M3D-ICs with 2D layered materials was first proposed by Kang et al. [15]. Despite some ...
Context 2
... semiconductor material family offers a wide range of properties with sizeable/controllable band gaps at atomiclevel thickness (Fig. 2), which led to the demonstration of various 2D logic devices [27]- [31] and circuits [32]. Additionally, intercalation-doped multilayer 2D materials in the form of doped-graphene-nanoribbon (DGNR) interconnect have been demonstrated as a promising candidate for next-generation interconnects that offers >50% interconnect thickness ...
Citations
... The sizable bandgap and dangling-bond-free surfaces, together with high carrier mobilities and excellent electrostatic control at the ultimate scale (less than 1 nm), make two-dimensional (2D) semiconductors ideal candidates for vertical 3D integration [1][2][3]37 . The prediction is that advanced monolithic 3D integrated circuits constructed with speedy layer-to-layer signal transmission and efficient heat dissipation will provide much higher integration density 38 . However, application-wise, 3D integrated circuits of 2D semiconductors have largely been restricted due to the difficulty in obtaining controllable doping of n-and p-type polarities, which is fundamental for complementary logic 34 . ...
Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis1–3. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures4,5, as well as hetero-2D layers with different carrier types6–8, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs. 9–17) and MoS2 (refs. 11,18–28)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm² V⁻¹ s⁻¹, on/off ratios reaching 10⁶ and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.
... Such 3D architectures not only overcome the scaling limitation with higher device density, but also enable new 3D computation systems, where multifunctional tiers (such as logic, memory and sensor) could be intimately collocated and vertically interconnected [15][16][17] . To date, one major challenge for silicon-based M3D integration is its low thermal budget, where the process temperature of upper tiers should not exceed the back-end-of-line temperature, typically less than 450 °C, to avoid performance degradation and dopant diffusion to lower tiers 3 . As silicon transistors need to be fabricated at a higher temperature, typically greater than 600 °C, the thermal budget limits the development of M3D integrated systems. ...
... Recently, two-dimensional (2D) semiconductors have demonstrated promising potential for M3D integration [1][2][3][4][5][6][7][8][9][10] . With dangling-bonds-free surfaces, 2D semiconductors could be presynthesized under relatively high temperature 18,19 and then physically transferred under a low processing temperature of below 200 °C (refs. ...
... However, assembly of multi-tier M3D systems using 2D semiconductors is a great challenge, because in M3D integration, each circuit tier consists of not only the semiconductor layer but also other active and passive layers, such as contacts, gate dielectrics, interconnects, inter-tier dielectric (ITD) and inter-tier vias (ITVs) that connect adjacent tiers 3,26 . In modern microelectronics, the integration of these functional layers is typically based on high-energy or high-temperature deposition processes, which are usually not compatible with the delicate 2D lattice with atomic thickness 11,12,[27][28][29] . ...
Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1–10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11–13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.
... This includes innovations in the ILD (see Supplementary Information section 7 for more discussion) and techniques such as CMP to reduce the impact of surface topography (see Supplementary Information section 8 for more discussion), which will reduce device-to-device and tier-to-tier variations. Moreover, for realizing larger circuits, parasitic capacitances must be minimized 39 , propagation delays must be reduced through innovation in interconnects and circuit and layout design 40 and thermal issues 41 must be mitigated by introducing spreaders and thermal vias among the layers in a 3D stack 42 (see Supplementary Information section 9 for more discussion). A detailed analysis of each of these aspects can become separate research topics and is beyond the scope of this work. ...
In the field of semiconductors, three-dimensional (3D) integration not only enables packaging of more devices per unit area, referred to as ‘More Moore’¹ but also introduces multifunctionalities for ‘More than Moore’² technologies. Although silicon-based 3D integrated circuits are commercially available3–5, there is limited effort on 3D integration of emerging nanomaterials6,7 such as two-dimensional (2D) materials despite their unique functionalities7–10. Here we demonstrate (1) wafer-scale and monolithic two-tier 3D integration based on MoS2 with more than 10,000 field-effect transistors (FETs) in each tier; (2) three-tier 3D integration based on both MoS2 and WSe2 with about 500 FETs in each tier; and (3) two-tier 3D integration based on 200 scaled MoS2 FETs (channel length, LCH = 45 nm) in each tier. We also realize a 3D circuit and demonstrate multifunctional capabilities, including sensing and storage. We believe that our demonstrations will serve as the foundation for more sophisticated, highly dense and functionally divergent integrated circuits with a larger number of tiers integrated monolithically in the third dimension.
... Consequently, the transistor-level abstraction style is ideal for M3D-IC implementation due to thermal constraints for reliability and better process control [17]. However, this style has reported increased MIV utilization due to the PMOS and NMOS device connections resulting in large silicon overhead around MIV. Additionally, with an increasing number of tiers in M3D-IC, power consumption increases significantly due to increasing tier thermal resistance [18]. Compared to traditional 2D implementation, M3D-IC has reported 2X static voltage droop (IR drop) due to increased connectivity in the bottom tiers and restricted routing of power MIVs due to top layer transistor placements [19]. ...
Transistor-level monolithic three-dimensional integrated circuit (M3D-IC) technology potential is compromised with the silicon footprint overhead caused by metal inter-layer via (MIV). To address this issue, we present a dual-purpose MIV-device utilization where MIV serves two purposes: 1. interconnect and 2. device terminal. A detailed study of the proposed MIV-devices specifically MIV-capacitor and MIV-transistor is performed and a strategy to extract level-3 Spice models is presented in this paper. Simulation results suggest that the basic logic gates designed with the opportunistic utilization of MIV-devices reduce the substrate utilization by up to 22% compared with the conventional transistor-level implementation in M3D-IC technology.
... CVD synthesis is typically carried out at an elevated temperature of around 1000 • C. The high-temperature solid-precursor CVD growth of MoS 2 is a deterrent for the 3D integration of semiconductor layers, making it a prospective alternative, as the lateral contraction of device features is at a limiting condition [20]. If MoS 2 logic devices are to be a viable alternative in 3D integration, compatibility between the initial and subsequent layers for deposition requires the low-temperature synthesis of MoS 2 thin films to reduce thermal stresses and restrict dopant as well as interfacial diffusion [21,22]. With 3D integration, MoS 2 monolayer Field Effect Transistors (FET's) can have high electron mobility, enabling faster switching speeds than traditional silicon transistors [23,24]. ...
Molybdenum disulfide (MoS2) transistors are a promising alternative for the semiconductor industry due to their large on/off current ratio (>1010), immunity to short-channel effects, and unique switching characteristics. MoS2 has drawn considerable interest due to its intriguing electrical, optical, sensing, and catalytic properties. Monolayer MoS2 is a semiconducting material with a direct band gap of ~1.9 eV, which can be tuned. Commercially, the aim of synthesizing a novel material is to grow high-quality samples over a large area and at a low cost. Although chemical vapor deposition (CVD) growth techniques are associated with a low-cost pathway and large-area material growth, a drawback concerns meeting the high crystalline quality required for nanoelectronic and optoelectronic applications. This research presents a lower-temperature CVD for the repeatable synthesis of large-size mono- or few-layer MoS2 using the direct vapor phase sulfurization of MoO3. The samples grown on Si/SiO2 substrates demonstrate a uniform single-crystalline quality in Raman spectroscopy, photoluminescence (PL), scanning electron microscopy (SEM), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and scanning transmission electron microscopy. These characterization techniques were targeted to confirm the uniform thickness, stoichiometry, and lattice spacing of the MoS2 layers. The MoS2 crystals were deposited over the entire surface of the sample substrate. With a detailed discussion of the CVD setup and an explanation of the process parameters that influence nucleation and growth, this work opens a new platform for the repeatable synthesis of highly crystalline mono- or few-layer MoS2 suitable for optoelectronic application.
... Relative to a collection of discrete circuit elements, ICs carry out operations more rapidly and use less energy. Recent advancements in IC design have led to the development of a three-dimensional (3D) IC configuration in which engineers vertically layer two-dimensional IC units [96]. This innovative design allowed construction of monolithic 3D ICs that contain within a single chip the necessary electronic components to carry out increasingly complex, advanced computational tasks [97]. ...
Over the last 75 years, artificial intelligence has evolved from a theoretical concept and novel paradigm describing the role that computers might play in our society to a tool with which we daily engage. In this review, we describe AI in terms of its constituent elements, the synthesis of which we refer to as the AI Silecosystem. Herein, we provide an historical perspective of the evolution of the AI Silecosystem, conceptualized and summarized as a Kuhnian paradigm. This manuscript focuses on the role that the AI Silecosystem plays in oncology and its emerging importance in the care of the community oncology patient. We observe that this important role arises out of a unique alliance between the academic oncology enterprise and community oncology practices. We provide evidence of this alliance by illustrating the practical establishment of the AI Silecosystem at the City of Hope Comprehensive Cancer Center and its team utilization by community oncology providers.
... This variability, coupled with minute changes in thickness, can lead to difficulties in achieving consistent and reliable device performance. 8 Additionally, the band gap of atomic-layer thick non-2D materials, such as Si or GaAs, would be far too large for most electronic applications. In contrast, 2D materials, such as graphene, TMDs, and other members of the Xene family, excel in the context of scaled up to chip integration and offer enhanced performance. ...
Current silicon technology is on the verge of reaching its performance limits. This aspect, coupled with the global chip shortage, makes a solid case for steering our attention toward the accelerated commercialization of other electronic materials. Among the available suite of emerging electronic materials, two-dimensional materials, including transition metal dichalcogenides (TMDs), exhibit improved short-channel effects, high electron mobility, and integration into CMOS-compatible processing. While these materials may not be able to replace silicon at the current stages of development, they can supplement Si in the form of Si-compatible CMOS processing and be manufactured for tailored applications. However, the major hurdle in the path of commercialization of such materials is the difficulty in producing their wafer-scale forms, which are not necessarily single crystalline but on a large scale. Recent but exploratory interest in 2D materials from industries, such as TSMC, necessitates an in-depth analysis of their commercialization potential based on trends and progress in entrenched electronic materials (Si) and ones with a short-term commercialization potential (GaN, GaAs). We also explore the possibility of unconventional fabrication techniques, such as printing, for 2D materials becoming more mainstream and being adopted by industries in the future. In this Perspective, we discuss aspects to optimize cost, time, thermal budget, and a general pathway for 2D materials to achieve similar milestones, with an emphasis on TMDs. Beyond synthesis, we propose a lab-to-fab workflow based on recent advances that can operate on a low budget with a mainstream full-scale Si fabrication unit.
... Monolithic three-dimensional integrated circuits (M3D-IC) are realized by sequential integration of ultra-thin substrate layers (thickness of 7nm -100nm) at low temperatures i.e., below 500 o C [1]. The thermal constraint of below 500 o C is levied on the M3D-IC process to ensure the stability of bottom-layer devices [2][3][4]. ...
Monolithic 3D integration has become a promising solution for future computing needs. The metal inter-layer via (MIV) forms interconnects between substrate layers in Monolithic 3D integration. Despite small size of MIV, the area overhead can become a major limitation for efficient M3D integration and, thus needs to be addressed. Previous works focused on the utilization of the substrate area around MIV to reduce this area overhead significantly but suffers from increased leakage and scaling factors. In this work, we discuss MIV-transistor realization that addresses both leakage and scaling issue along with similar area overhead reduction compared with previous works and, thus can be utilized efficiently. Our simulation results suggest that the leakage current $(I_{D,leak})$ has reduced by $14K\times$ and, the maximum current $(I_{D,max})$ increased by $58\%$ for the proposed MIV-transistor compared with the previous implementation. In addition, performance metrics of the inverter realization with our proposed MIV-transistor specifically the delay, slew time and power consumption reduced by $11.6\%$, $17.9\%$ and, $4.5\%$ respectively compared with the previous implementation with same MIV area overhead reduction.
... 3D ICs promise a smaller form factor, higher integration density, lower power consumption, better signal integrity, and heterogeneous integration compared to conventional 2D ICs. Utilizing both a 2D TMD channel and the finFET design into 3D ICs can combine their respective advantages 11,13,14 ; however, the intuitive question is whether 2D materials-based devices and their fabrication are compatible with existing Si-based semiconductor technology. This question has yet to be examined, although 2D materials and related devices have been broadly studied in academia. ...
... Therefore, incorporating 2D materials into 3D ICs is considered difficult by using conventional TSV-based 3D integration. Auspiciously, monolithic 3D ICs (M3D ICs), enabled by sequential integration of device tiers on the same wafer by deposition or recrystallization, is a relatively feasible strategy for incorporating 2D materials in 3D ICs 11,13,17 . The high process temperature used during the sequential processes should, nevertheless, be prevented to reduce the thermal budget and to avoid affecting the performance of the lower layer active devices. ...
The performance enhancement of integrated circuits relying on dimension scaling (i.e., following Moore’s Law) is more and more challenging owing to the physical limit of Si materials. Monolithic three-dimensional (M3D) integration has been considered as a powerful scheme to further boost up the system performance. Two-dimensional (2D) materials such as MoS 2 are potential building blocks for constructing upper-tier transistors owing to their high mobility, atomic thickness, and back-end-of-line (BEOL) compatible processes. The concept to integrate 2D material-based devices with Si field-effect transistor (FET) is technologically important but the compatibility is yet to be experimentally demonstrated. Here, we successfully integrated an n-type monolayer MoS 2 FET on a p-type Si fin-shaped FET with 20 nm fin width via an M3D integration technique to form a complementary inverter. The integration was enabled by deliberately adopting industrially matured techniques, such as chemical mechanical planarization and e-beam evaporation, to ensure its compatibility with the existing 3D integrated circuit process and the semiconductor industry in general. The 2D FET is fabricated using low-temperature sequential processes to avoid the degradation of lower-tier Si devices. The MoS 2 n-FETs and Si p-FinFETs display symmetrical transfer characteristics and the resulting 3D complementary metal-oxide-semiconductor inverter show a voltage transfer characteristic with a maximum gain of ~38. This work clearly proves the integration compatibility of 2D materials with Si-based devices, encouraging the further development of monolithic 3D integrated circuits.
... Along this route, two-dimensional (2D) semiconductors, among other contenders such as carbon nanotubes (CNT), nanowires, and III-V compound semiconductors, are considered promising for both "More Moore" and "More than Moore" technologies. In fact, it is even numerically analyzed and proposed that 2D materials have the potential to take full advantage of 3D integration [10]. ...
Three-dimensional (3D) integration is an emerging technology that is revolutionizing the semiconductor industry. On one hand, it enables the packaging of more devices per unit volume, also referred to as “More Moore”, while on the other hand, it empowers multifunctionality, also known as “More than Moore”, both of which are key toward the development of low-cost, energy-efficient, and high-performance smart electronic systems. While silicon-based 3D integrated circuits (ICs) are already commercially available, there is limited effort on 3D integration of emerging nanomaterials such as two-dimensional (2D) materials despite their novel functionalities that may benefit many applications. Here we demonstrate monolithic 3D integration of a large volume (in excess of 600 transistors in each tier) of aggressively scaled field effect transistors (FETs) based on monolayer MoS2 at low-thermal budget (with processing temperature < 185 °C). We also realize 3D circuits and demonstrate multifunctional capabilities including sensing, memory storage, as well as logic gates in any tier across the 3D stack. We believe that our demonstration will pave the path for more sophisticated, highly dense, and functionally divergent ICs with a larger number of tiers integrated monolithically in the third dimension.
