Figure 2 - uploaded by Saraju P. Mohanty
Content may be subject to copyright.
(a) Schematic diagram of the proposed 2-port 6T SRAM bitcell with shared read and write assist transistors per word (b) the voltage transfer characteristics and SNM obtained from butterfly curve for the standard 8T, 7T and proposed 6T SRAM bitcells.
Source publication
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on a chip (SoC) technology. Hence, simultaneous or parallel read/write (R/W) access multi-port SRAM bitcells are widely employed in such embedded systems. In this paper, we...
Contexts in source publication
Context 1
... standard 8T, stability issues are quite similar to 1-port 6T bitcell such as conflicting read and write requirements of sizing the pass-gate devices, as a result large bitcell size. Handling of parametric yield loss due to stability issues or a poor read SNM, as shown in Figure 2(b), and WAM simultaneously in the standard 2-port 8T bitcell is a challenging task, because of tuning the cell ratio (β) of both the ports, while, maintaining adequate I read . The I read (read-current path shown in dotted) has direct interven- tion with the data storage node and a strong relationship with the read SNM and read access time (performance). ...
Context 2
... eliminates the conflicting read and write re- quirements of sizing of pass-gate access devices which exist in standard 1-port 6T and 2-port 8T bitcells, thus device sizes can be optimize separately for target margins to achieve a delicate balance between read stability and write-ability. The isolation of read-ports provides more than 2 times better read SNM that cannot be achieved in standard 6T bitcell, as shown in Fig- ure 2(b). Maintaining a strong write-ability of logic '1' is dif- ficult, specifically when a single ended write bitline and a pass gate device are used. ...
Similar publications
![a Power dissipation as a function of Vbs\documentclass[12pt]{minimal}...](publication/327169483/figure/fig3/AS:960484673064981@1606008799945/a-Power-dissipation-as-a-function-of-Vbsdocumentclass12ptminimal_Q320.jpg)
Stability of memory cells always considered as a most significant figure for defining the logic data at output terminals. And the value of logic data is influenced due to the dominance of leakage component at deep submicron technology. Stability analysis and leakage issues of new 9T adiabatic static random access memory (SRAM) cells is presented us...
This paper proposes a novel memory architecture
called VP SRAM-based TCAM (Vertically Partitioned Static
Random Access Memory based-Ternary Content Addressable
Memory) that emulates TCAM functionality with SRAM.VP
SRAM-based TCAM dissects conventional TCAM table
vertically (column-wise) into TCAM sub-tables, which are then
processed to be stored in...
STT-RAM (Spin Transfer Torque Random Access Memory) has been extensively researched as a potential replacement of SRAM (Static RAM) as on-chip caches. Prior work has shown that STT-RAM caches can improve performance and reduce power consumption because of its advantages of high density, fast read speed, low standby power, etc. However, under the im...
This paper proposes a novel and an efficient method termed hypersphere sampling to estimate the circuit yield of low-failure probability with a large number of variable sources. Importance sampling using a mean-shift Gaussian mixture distribution as an alternative distribution is used for yield estimation. Further, the proposed method is used to de...
As memory density continues to grow in modern systems, accurate analysis of static RAM (SRAM) stability is increasingly important to ensure high yields. Traditional static noise margin metrics fail to capture the dynamic characteristics of SRAM behavior, leading to expensive over design and disastrous under design. One of the central components of...
Citations
... Different design methods have been proposed, such as dualthreshold voltage (V T h ) assignment, and decrease in supply voltage, which reduces the dynamic power quadratically and reduces the leakage power linearly [1]. However, substantial problems have been noted when the traditional six-transistor SRAM cell is subjected to ultra-low voltage supply as it demonstrates poor stability [2]. As process technology scales deeper, the demand for increased integration density and improved device performance is also increasing [3]. ...
... Research Power SNM Technology Temperature Technique Agrawal [5] – 160 mV (approx.) 65 nm – Modeling based approach Liu [6] 31.9 nW 300 mV 65 nm 70 • C Separate data transistors Kulkarni [7] 0.11 µW (leakage) 78 mV 130 nm 27 • C Schmitt trigger Lin [8] 4.95 nW (standby) 310 mV 32 nm 25 • C Separate read mechanism Bollapalli [9] 10 mW (total) – 45 nm – Separate word line groups Azam [10] 63.9 µW 299 mV 45nm – Separate read/write assist circuitry Singh [2] 2.6 µW (total) – 65nm 27 • C Two-port 6TSRAM with multiport capabilities Thakral [1] ...
... Initially, the logical design is performed for the 7T cell. The 7T single-ended SRAM (SE-SRAM) is well known for its potential of low active power and leakage dissipations [2]. From this design, baseline parameters are measured such as average power consumption (including subthreshold leakage and gate oxide leakage) and SNM. ...
Low power consumption, stability, and PVT-tolerance in Static Random Access Memories (SRAM) is essential for nanoscale System-on-Chip (SoC) designs. In this paper, a novel design flow is presented for optimizing a figure of merit called Power to Static-Noise-Margin (SNM) Ratio (PSR). The minimization of PSR results in power minimization and SNM maximization of nano-CMOS SRAM circuits which are mutually conflicting objectives. A 45 nm single ended 7-Transistor SRAM is used as an example circuit for demonstrating the effectiveness of the optimal design flow presented in this paper. Worst case temperature analysis is performed on a baseline SRAM circuit for all three Figures of Merit (FoMs): power, SNM, and PSR. After accurate characterization of the FoMs for worst case temperature and process variation analysis, the baseline SRAM circuit at worst case temperature is subjected to a polynomial regression based optimization algorithm. Simulation results demonstrate that the optimal SRAM design is PVT-tolerant with optimized power consumption, SNM and PSR.
... However, it is not optimized for small memories and includes overhead like redundancy. Using technology parameters for SRAM [24, 28], eDRAM [15] and flash [17], we computed lower bounds on area as follows. Using transistor counting, we estimate control logic overhead (decoders, sense amps, drivers) as 50% area per bit, which correlates with data in [15]. ...
Modern FPGAs are used to implement a wide range of circuits, many of which have coarse-grained and fine-grained components. The ever-increasing size of these circuits places great demand on CAD tools to synthesize circuits faster and without loss in quality. Synthesizing coarse-grained components onto fine-grained FPGA resources is inefficient, and past attempts to optimize FPGAs for word-oriented datapaths have met with limited success. This paper presents a CAD flow to fully compile Verilog into a configuration bitstream for a new type of FPGA with time-multiplexed coarse-grained resources. We demonstrate two approaches with gains of 61x and 42x in synthesis time on average compared to QuartusII, but due to time-multiplexing and current synthesis limitations we achieve circuit speeds of 14x and 8.5x slower on average. We show the tools can also trade density for maximum clock frequency.
This paper presents on the analysis of static and dynamic power dissipations in the proposed 10T SRAM cell. In the proposed structure two voltage sources, one connected with the Bit line and the other connected with the Bit bar line for reducing the voltage swing during the switching activity. This reduction in voltage swing causes less dynamic power dissipation during switching activity. Two stack transistors are also connected in the pull-down paths which result in increase in the threshold voltage of the transistors and thus cause the reduction in static power dissipation. Simulation has been done in 90nm CMOS technology with 1 volt power supply in Microwind 3.1 software. Simulation results have been compared with those of other existing SRAM cells.
This paper proposes a two-write and two-read (2W2R) bit-cell for a multi-port (MP) SRAM design to improve the static noise margin (SNM) and solve the write-disturb issues of nanoscale CMOS technologies. Using an additional Y-access MOS (column-direction access transistor), the
2W2R MP SRAM adopts a scheme of combining the row access transistor and sharing write bit-line with an adjacent bit cell. This scheme halves the write bit-line number and mitigates the write current consumption caused by pre-charging the bit-line to V
DD. This paper also proposes
a selective read path structure for read operation. Replacing the ground connection in the read port with a virtual V
SS controlled by a Y-select signal reduces read-port current consumption. Results show that the proposed design reduces both the write current and read
current consumption by 30%, compared to the conventional MP structure, from 1.3 V to 0.6 V V
DD. The proposed 8 Kb 2W2R MP SRAM was fabricated on the test chip using TSMC 40 nm CMOS technology.
This paper combines several low-leakage and low-cost techniques to design multi-port static random access memory (SRAM) for register file in a vertex shader processor for OpenGL ES 2.0 graphics applications. First, precharge control is employed to eliminate unnecessary precharge operations. Then, dynamic forward body-bias control for leakage reduction is proposed to adjust the threshold voltage of transistors depending on whether memory cell is accessed or idle. Different power-gating methods are presented for SRAM cells and for sense amplifiers. The thin-cell-like lithography-friendly layout style is adopted for the multi-port SRAM cell to achieve more compact and flexible layout with easy addition of read ports. The cross-coupled inverters in the SRAM cell have asymmetric design to reduce area and also increase the writability. A 32×128-bit register file supporting 5-read and 1-write operations is implemented and verified, which has smaller area and lower leakage compared with that from ARM register file generator.
Multi-port SRAMs are essential for caches and shared data structures, especially in modern multi-core SoCs. The FinFET device, which offers high threshold voltage and high on/off current ratio, is a promising candidate for multi-port SRAMs for fast read/write speed, high cell density, and low power consumption. In this paper, we perform the first study of multi-port FinFET SRAMs, including the double-ended multi-port FinFET SRAM and three single-ended multi-port FinFET SRAMs with isolated read ports. We evaluate the static noise margin, leakage current, and read/write performance of these structures with the predictive technology model for FinFETs. Our results show that single-ended multi-port FinFET SRAMs with isolated read ports offer improved read stability and flexibility over the double-ended structure at the expense of write performance. By increasing the size of the access transistors, we show that the single-ended structures can achieve equivalent write performance to the double-ended structure for 9% area overhead.
This brief proposes one-write–one-read (1W1R) and two-write–two-read (2W2R) multiport (MP) SRAMs for register file applications in nanoscale CMOS technology. The cell features a cross-point Write word-line structure to mitigate Write Half-Select disturb and improve the static noise margin (SNM). The Write bit-lines (WBLs) and Write row-access transistors are shared with adjacent bit-cells to reduce the cell transistor count and area. The scheme halves the number of WBL, thus reducing WBL leakage and power consumption. In addition, column-based virtual ${rm V}_{rm SS}$ control is employed for the Read stack to reduce the Read power consumption. Post-sim results show that the proposed scheme reduces both Write/Read current consumption by over 30% compared with the previous MP structure. The proposed scheme is demonstrated and validated by an 8-Kb 2W2R SRAM test chip fabricated in TSMC 40-nm CMOS technology.
As transistor dimensions are reduced due to technological advances, the area constraint is becoming less restrictive, but soft error rate, leakage current, and process variation are drastically increased. Therefore, in nano-scaled CMOS technology, soft error rate, leakage current and process variation are the most important issues in designing embedded cache memory. To overcome these challenges, and based on the observation that cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper deals with new low leakage, hardened, and read-static-noise-margin-free SRAM memory cells for nano-scaled CMOS technology. These cells are completely hardened and cannot flip from particle strikes at the sensitive cell nodes. Furthermore, these new SRAM cells have free read-static-noise-margin, such that transistor mismatching, due to process variation, cannot destroy stored-data of the cells during read operation. The new cells retain their data with leakage currents and positive feedback without a refresh cycle. The basic version of new cells consists of one write port with differential write-bit-lines and one read port with differential read-bit-lines, and the improved-leakage version of new cells consists of one write port with differential write-bit-lines and one read port with a single read-bit-line. Simulation results show that the proposed cells in this work correctly operate during their read, write, and idle cycles even while considering the process variation in 22-nm technology. In the worst case, our cells have 40% lower average leakage current in comparison with conventional 6T SRAM cell without any performance degradation. Also, our cells are hardened. Thus, they have zero soft error rate.
As technology continues to scale, maintaining important figures of merit of Static Random Access Memories (SRAMs), such as power dissipation and an acceptable Static Noise Margin (SNM), becomes increasingly challenging. In this paper, we address SRAM instability and power (leakage) dissipation in scaled-down technologies by presenting a novel design flow for simultaneous power minimization, performance maximization and process variation tolerance (P3) optimization of nano-CMOS circuits. The 45 and 32 nm technology node standard 6-Transistor (6T) and 8T SRAM cells are used as example circuits for demonstration of the effectiveness of the flow. Thereafter, the SRAM cell is subjected to a dual threshold voltage (dual-VTh) assignment based on a novel statistical Design of Experiments–Integer Linear Programming (DOE–ILP) approach. Experimental results show 61% leakage power reduction and 13% increase in the read SNM. In addition, process variation analysis of the optimized cell is conducted considering the variability effect in twelve device parameters. To the best of the authors' knowledge, this is the first study which makes use of statistical DOE–ILP for optimization of conflicting targets of stability and power in the presence of process variations in SRAMs.
This paper describes the FPGA implementation of FastCrypto, which extends a general-purpose processor with a crypto coprocessor for encrypting/decrypting data. Moreover, it studies the trade-offs between FastCrypto performance and design parameters, including the number of stages per round, the number of parallel Advance Encryption Standard (AES) pipelines, and the size of the queues. Besides, it shows the effect of memory latency on the FastCrypto performance. FastCrypto is implemented with VHDL programming language on Xilinx Virtex V FPGA. A throughput of 222 Gb/s at 444 MHz can be achieved on four parallel AES pipelines. To reduce the power consumption, the frequency of four parallel AES pipelines is reduced to 100 MHz while the other components are running at 400 MHz. In this case, our results show a FastCrypto performance of 61.725 bits per clock cycle (b/cc) when 128-bit single-port L2 cache memory is used. However, increasing the memory bus width to 256-bit or using 128-bit dual-port memory, improves the performance to 112.5 b/cc (45 Gb/s at 400 MHz), which represents 88% of the ideal performance (128 b/cc).
