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The most timing critical part of logic design usually contains one or more arithmetic operations,
in which addition is commonly involved. In VLSI applications, area, delay and power are the important factors
which must be taken into account in the design of a fast adder [1]. The paper attempts to examine the features
of certain adder circuits which...
Citations
... There are various adders [12] [10] [8] [14] invented so far like Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA), Carry increment Adder (CIA), Carry Skip Adder (CSKA) [13] [16] , Carry Save Adder (CSA) [10], Carry Select Adder (CSLA) etc. The simplest adder is the RCA. ...
... Carry skip adder (CSkA) [13,15,17] is very effective in higher bit operation as it can skip the carry for the next block. If there is no carry propagation delay for the circuit then it will help to reduce the total gate delay. ...
... The power consumption, delay time, and power-delay product (PDP) of proposed 8-bit CSLA are compared with 8-bit R-CSLA and M-CSLA. The results of proposed 8-bit CSLA are also compared with the 8- bit CSA proposed in recent studies [14, 15]. The comparison is shown in ...
... C out Advances in Electronics 5 The postsimulation input-output waveforms for the 8-bit proposed CSLA are shown in Figures 6 and 7, respectively. The proposed design is simulated with a 12.5 MHz waveform with rise and fall times of 4 ns.Figure 8 shows the comparison of various carry select adders in graphical form for the data given inTable 2. We can see from the graph that the proposed CSLA has minimum power-delay product (PDP) as well as the minimum power consumption when compared with regular CSLA, modified CSLA [10], CSLA [14], and reversible logic style based 8-bit CSA [15]. ...
In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA.
In today’s enhanced technological advancements, a carry select adder performs an indispensable integral part of the complex processing of data. It exhibits promising results in minimizing cost and power consumption. The logic operation of it has simulated over 90 nm CMOS technology of spice tool at 0.8 V. These works present a Carry select adder using multiplier and adder circuits. In proposed designs, extra circuitry is eliminated and leads to a reduction in 43.995% of power consumption, 93.912% of time delay, and 97.515% of energy. The transistor count of the proposed carry select adder is 61.788% less than that of the conventional carry select adder. The power, delay, energy of it has been compared with state-of-art carry select adder. This advanced circuit of adder shows highly efficient and reliable performance.
An adder is a fundamental component of various Very Large-Scale Integration (VLSI) circuits like Central Processing Unit (CPU), Arithmetic Logic Unit (ALU), Memory Access Unit (MAU) etc. A various number of operations can be achieved by adders such as addition, subtraction, multiplication, division, exponentiation etc. The basic circuit of the adder is designed using logic gates. The demand for high-performance VLSI systems are increasing rapidly for use in small and portable devices. The speed related to operation depends upon the delay of the adder as it happens to be one of the most fundamental components of all the computing units and it is a very important parameter for high performance. There have been so many research works on reducing the delay associated with the adder. In this paper, we have done a comparative study of Carry Save Adder (CSA) and Carry Increment Adder (CIA) and proposed a hybrid adder circuit to decrease the delay associated with the adder to an optimum level. As CIA has favorable performance regarding propagation delay and CSA also happens to have good performance in higher bit operations. A simulation study has been carried out for comparative study, the coding has been done using Verilog hardware description language (HDL) and the simulation has been realized with the help of Xilinx ISE 14.7 environment. The result shows the effectiveness of the hybrid circuit proposed for propagation delay improvement.
It is profoundly accepted that the main processing unit of any device capable of carrying out computations is the Central Processing Unit (CPU) and the one of the most fundamental and integral part of CPU is an Arithmetic and Logical Unit (ALU) and adders are the primary and indispensable component of Arithmetic Logic Unit (ALU). The ALU is primarily responsible for carrying out the logical operation, arithmetic operations etc. Adders are also very important for Digital Signal Processing (DSP) for filter designing. Nowadays it has become very important to speed up all devices and make them more power efficient for lack of storage of huge amount of power and small in size for mobility. As adders are the main part of all these, it is of prime importance that we modify the adder in order to fetch maximum efficiency regarding – Propagation delay, Area on Chip and Power Consumption. Various adders have been invented so far which specializes in various work platform and they are efficient in their ways. This paper consists a comparative study on various parallel adders and proposes a hybrid adder. All the results of the Adders are carried out in Xilinx 14.7 ISE environment and coded using Verilog HDL. Specific graph and table of the values are given for propagation delay, area, number of transistors required for a better comparison.
Adders are one of most essential components of the digital circuits that are designed for different DSP applications. The important aspects considered for designing any digital circuit design are delay, power and Power Delay Product (PDP). In this paper, 32 bit carry bypass adders (CBA) which have superior performance with respect to these parameters are presented. The CBA's are implemented using different block structures such as 2 block, 4 block, 8 block and 16 block. These different carry bypass adders are designed using 90 nm CMOS technology and are implemented using Cadence Virtuoso software. The simulation results indicate that compared to existing CBA circuits, the proposed CBA circuits have better power, delay and PDP characteristics. Also the voltage degradation issues observed in other existing CBA circuits are not observed in the proposed carry-bypass adders. So the proposed CBA circuits can be used in practical DSP applications.
The adders are basic building blocks of the digital circuits for the Signal processing, Integrating and other process of operation. There are various types of adders are proposed in Literature which are commonly used in VLSI Design. The Ultimate aim of the VLSI Design is to reduce the number of gates, power, Delay and they are the Important factors which are taken in consideration. In this Paper a comparative analysis of Speed, Power consumption, Area and Power delay Product (PDP) are implemented for design of Carry Skip Adder with other adders as Ripple Carry Adder and Parallel Prefix Adders. The Simulation results also shows that the proposed adder is Faster and Area efficient compared to other adders. They estimates the performance of proposed design will be better in terms of Logic and route delay by experimental results.
