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This paper presents an RTL-level model of an 8B/10B encoder/decoder block in SystemC. The use of 8B/10B coding is an important technique in the construction of high performance serial interfaces. These are particularly suitable for alleviating the I/O bottleneck of state of the art systems (which are pinout, rather than bandwidth limited). SystemC...
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... received code are decoded based on the running disparity process, as previously stated. The block diagram of the decoder module is shown in Figure (4). Latency for this modules is the same as for the encoder; i.e. 5 cycle latency, after which the decoded data is passed to the decoder output port and collected by stimulus process. ...
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This study proposes an improved Hybrid Network‐on‐Chip (HNoC) with a flexible topology and frugal routing. The key advantage is in terms of latency and saturation because of the optimal use of RF‐based wireless networks. The performance improvement is achieved by managing the communication resources through a radio bandwidth allocation algorithm an...
At high abstraction level, multi-processor system-on-chip (SoC) designs are specified as assembling of IP's which can be hardware or software. The refinement of communication between these different IP's, known as hardware/software interfaces, is widely seen as the design bottleneck due to their complexity. In order to perform early design validati...
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... For example, four symbol durations can be used to encode "00", "11", "01", and "10" bit patterns in the signature. In addition, both hardware and software integrity verification systems can use the well-known 8b/10b encoding algorithm [24] to minimize distortion of the emitted waveform by ensuring DC balance. ...
Modern microelectronics life-cycle and supply chain ecosystem bring multiple untrusted entities, which can compromise their integrity. A major integrity issue of microelectronics stems from piracy of intellectual properties (IP) and counterfeiting, which causes significant revenue loss to the semiconductor manufacturers. Further, these components often lead to compromised functionality, reliability, security, and safety of an electronic system. This paper presents secure information transmission and probing methods for verifying the integrity of digital integrated circuit (ICs) based on their electromagnetic (EM) near-field emissions and thereby protecting systems against counterfeit components. The proposed method has been tested on both high-level instructions executed by microprocessors or Systems-on-Chip (serving as examples of software), and also logic circuits within FPGA fabrics and ASICs (serving as examples of hardware). The authentication information required by each digital system is generated using a pseudo-random number generator circuit and securely transmitted via near-field magnetic emissions. The authorized party can probe these emissions using a near-field probe, process the acquired signals to improve the signal-to-noise ratio (SNR), and then recover the secure information through matched filtering. Experimental results from commercial SoCs are used to demonstrate the proposed technique. Methods for reducing EM interference during integrity verification of both FPGAs and ASICs are also described.
... The IEEE-1666 SystemC [5] standard enables systems, software and hardware designers to model complex SoC platforms [33,52,11,172] thanks to a large set of language primitives. Many of these language primitives enable the synchronization of the data being modeling. ...
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The market for Internet Of Things (IOT) is on the rise. It is predicted to continue to grow at a sustained pace in the coming years. Connected objects are composed of dedicated electronic components, processors and software. The design of such systems is today a challenge from an industrial point of view. This challenge is reinforced by market competition and time tomarket that directly impact the success of a system. In a current design process involvesthe development of a specification. Initially, the team in charge of hardware development beginsto design the system. Second, the application part can be done by software developers. Oncethe first hardware prototype is available, the software team can then integrate their part and try tovalidate the functionality. This step may reveal defects in the software but also in the hardware architecture. Unfortunately, the discovery of these errors occurs far too late in the design process,could impacts the marketing of the system and potentially its success. In order to ensure that the hardware and software designs will work together as early as possible, methodologies based onthe SystemC / Transaction Level Modeling (TLM) standard have been widely adopted. They involvethe modelling and simulation of the proposed hardware architectures. During the initial phasesof a product’s design, they enable the software and hardware team to share a virtual version ofthe (future) system. This virtual version is more commonly referred to as a virtual platform. It facilitates early software development, test and validation; reduces material cost by limiting the number of prototypes; saves time and money by reducing risks. However, connected objects are increasingly incorporating hardware and software features. As the requirements have evolved, theSystemC / TLM simulation standard no longer meets all expectations. It includes aspects related to the simulation of systems composed of many functionality, disparate communication protocolsbut also complex and time consuming models during the simulation. Some works have already been carried out on these subjects. However, as the number of components increases, all formsof interoperability of models and tools become increasingly difficult to handle. Moreover, mostof the research has resulted in solutions that are not inter-operable and can not reuse existingmodels. To solve these problems, this thesis proposes a solution for configuring SystemC / TLMmodels. It is now part of the standard Configuration, Control and Inspection (CCI). In a secondstep, the modeling of high-level abstraction communication protocols (TLM Loosely Timed (LT)and Approximately Timed (AT)) has been studied, as it relates to non-bus protocols. An evolution of the standard to improve support, interoperability and reuse is also proposed. In a third step,a change of the SystemC standard and more precisely of the behavior of the simulation kernelhas been studied to support asynchronous events. These open the way to parallelization and distribution of models on different threads / machines. In a fourth step, a solution to integrate Central Processing Units (CPU) models integrated in Quick EMUlator (QEMU), a system emulator/ virtualizer, has been studied. Finally, all these contributions have been applied in the modeling ofa set of objects connected to a gateway.
... To achieve the uniformity of the consumption current and completely remove the supporting regulator, we focus on the coding techniques to control the number of I=O switchings, as shown in Fig. 4. We first focus on the two following conventional coding methods: (a) 8B=10B coding and (b) bus-invert coding. [25][26][27][28] 2.1 8B/10B coding 8B=10B coding is commonly performed in optical and highspeed serial interfaces. It can generate a special code in which an almost 50% existence probability of "1"s is guaranteed by converting an 8-bit input code to a corresponding 10-bit output code. ...
... Figures 5(a) and 5(b) show a block diagram and sample codes for 8B=10B coding, respectively. 25,26) The 8-bit input code is divided into 3-and 5-bit codes, which are then converted to 4-and 6-bit codes. To control the existence of the "1"s in the code sequence, the disparity controller mixes the 4-and 6-bit codes depending on the running disparity (RD). ...
Two new parallel bus coding methods for generating a DC-balanced code with additional bits are proposed to achieve the self-stabilization of the intermediate power level in Stacked-Vdd integrated circuits. They contribute to producing a uniform switching current in parallel inputs and outputs (I/Os). Type I coding minimizes the difference in the number of switchings between the upper and lower CMOS I/Os by 8B/10B coding followed by toggle conversion. Type II coding, in which the multi-value running disparity control feature is integrated into the bus-invert coding, requires only one redundant bit for any wider bus. Their DC-balanced feature and the stability effect of the intermediate power level in the Stacked-Vdd structure were experimentally confirmed from the measurement results obtained from the developed test chips.
... In the past decade, the protocol has become a hot topic of the researchers. Many hundreds of papers have been published on the various fields in FC, which include the simulation of the network performance based on FC [3,4] and the architecture of software in FC adaptors [5,6] and the encoder and decoder in FC physical layer [7,8] and the testing methods of FC appliances [9,10] and the future of FC [11,12] and so on. Today, although many other technologies in SNA appear, for example InfiniBand and iSCSI (Internet small computer system interface), FC is still a standard solution in storage area network, especially in enterprise datacenters. ...
Fiber channel (FC) has become a major technology in Storage area network (SAN), especially in enterprise datacenters. In this paper, we propose a config-urable and all-around architecture to implement the FC-1 and FC-2 layers in VLSI. The speed negotiation algorithm is also implemented in hardware to automatically switch speed among 4 different speeds. In order to achieve the on-the-fly processing speed, we utilize the hardware to ac-celerate the processing of FC-1 and part of FC-2. The prototype chip is fabricated in a 0.18um CMOS technol-ogy and the core occupies an area of 7.1 × 8mm 2 . The chip has been validated to be fully functional and can achieve 173MBps processing performance.
... In the past decade, the protocol has become a hot topic of the researchers. Many hundreds of papers have been published in almost all fields of the Fiber Channel, including the architecture of protocol software in FC adaptors, simulation of the network performance based on FC, the 8B/10B en/decoder [4] [5] in FC physical layer and the implementation of FC [6][7][8][9] and so on. However there is almost no paper referring to the clock synchronization of FC. ...
... The clock synchronization is attained by passing Primitive Signals (SYNx, SYNy, SYNz) to clients just as the following Fig.3 and the format of Primitive Signals is as the Fig.4. The clients need to decode the 48 bits neutral disparity [4][5] characters CS_X, CS_X', CS_Y, CS_Y', CS_Z, CS_Z' in Primitive Signals to the 42 bits binary data. And the 42 bits binary data is clock synchronization data. ...
In this paper, we introduce two methods to implement clock synchronization in fiber channel. One is based on ELS (extended link service) transmission and the other is based on primitive signal transmission. Compared with the method based on ELS transmission, the primitive method is at least 20 times faster and consumes less power. Furthermore, we propose an area efficient method to implement encoding and decoding procedure between neutral disparity character and binary clock synchronization data in primitive clock synchronization scheme. Utilizing the proposed method, we can reduce the area by 50.2% in decoding and 26.7% in encoding. At last, we implemented the primitive clock synchronization method in prototype chip fabricated in a 0.18 mum CMOS technology with six layers of metal and functioned well.
This paper describe a byte oriented transmission code and its hardware implementation with elaborating a method for implementation of the DC-balanced 8B/10B coding using a very fast FPGA from Spartan family. This code is particularly well suited for high-speed local area networks. This technique can be used by other high speed buses such as PCI Express, IEEE 1394b, Serial ATA, SAS, Fiber channel, SSA. Gigabit Ethernet INFIBAND, XAUI, Serial Rapid IO, uses the same coding module. Using the Look-up Table and memory with fast technique made this design efficient to be implemented. A very simple implementation of the code has been accomplished by the partitioning of the coder into 5B/6B and 3B/4B subordinates coders. For increasing its performance more RTL logic is required.
In this paper, we propose and compare two architectures of HW/SW interface logic in FC-2, namely as TX/RX scheduler and TX/RX controller. The comparison result shows that the TX/RX controller is more efficient than the TX/RX scheduler. The TX/RX controller is implemented in the proto Fiber Channel (FC) chip fabricated in a 0.18um CMOS technology with six layers of metal. The gate count of TX/RX controller is about 10887 gates and the highest throughput of FC chip is 173MBps. In order to further improve the performance of FC, we propose an improved TX/RX controller based on the implemented one. The two interface logics are thoroughly tested in different test cases and the result shows that the improved one can improve the performance by 2~5 times at the cost of 1.8 times area increased.
SystemC is established as a suitable design and modelling language. It provides a consistent methodology for the design and refinement of complex digital systems. This paper focuses on how wireless features can be incorporated into existing SystemC design methodology in order to use this methodology to model wireless systems. The SystemC modelling language currently lacks a standard framework that supports modelling of wireless communication systems (particularly the use of wireless communication channels). Three components must be investigated in order to achieve this target: the development of a system level model of a digital wireless communication channel that represents the core of any communication system, the creation of a small library of dedicated elements at system level, such as PLL (Phased Locked Loop), 8B/10B Encoder/Decoder and several communication protocols modelling, and a case study/demonstration validating wireless extension methodology. The first two parts have been modelled successful, so we now focus on modelling a flocking behaviour system and demonstrating how these parts integrate to achieve the target.
The current SystemC modelling language lacks a standard framework that supports the modelling of wireless communication systems. This research investigates how wireless features can be incorporated into existing SystemC design methodology. The components to be investigated in order to achieve this target are divided into three parts: developing a system-level model of a digital wireless communication channel, creating a small library of dedicated elements at system level, and concluding with a case study on flocking behaviour system to validate the wireless extension methodology. In previous works, all these parts were successfully modelled and implemented. In this paper, the integration of communication modelling is introduced into design modelling during the early stages of system development. We use a flocking behaviour system to show how the stability of the system and converging point are measured and optimised in terms of system construction, using some important concepts of graph theory.
