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Three-Independent-Gate Field Effect Transistors (TIGFETs) are a promising next-generation device technology. Their controllable-polarity capability allows for superior design of arithmetic and sequential logic gates. In this article, TIGFET technology has been benchmarked against several beyond-CMOS devices. The benchmarking techniques followed a s...
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... functionality of TIGFET transistors enable a straight- forward implementation of the 1-bit full adder. It requires three inverters, one three-input XOR gate and one three-input MAJ gate as depicted in Fig. 6. The three inverters invert A, B, and carry-in (Cin) while the XOR gate outputs Sum and the MAJ gate outputs carry-out (Cout). The area of the 1-bit full adder is then shown to be: ...
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... first important metric that is evaluated in BCB 3.0 [9] is the 32-bit adder. Here, we adopt a unique design for the 32-bit ripple-carry adder utilizing TIGFET transistors. Indeed, every stage, depicted in Fig. 7(a), relies on the efficient TIGFET 1- bit full adder design (Fig. 6) to generate Sum n and Cout n but adds an extra three-input MAJ gate to generate Cout n . Generating both Cout n and Cout n at the same logic level is made possible by the TIGFET technology at a low additional area cost (only two more transistors per stage) and leads to a significant performance benefit. The general structure of the 32-bit adder is shown in Fig. ...
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... 1-bit full adder, as presented in Fig. 6, is designed using one XOR gate and one MAJ gate. The expression of the energy component, E 1bit , is estimated using the activity factor found in [34] and [35]. The activity factor of the three- input XOR (α xor3 ) and of the three-input MAJ (α maj3 ) are calculated to be 3/16 and 1/4, respectively. Furthermore, the unique structure of a TIGFET full adder allows the delay, t 1bit , to be dependent on a single tile plus an inverter. The standby power, S 1bit , includes two tile and three inverter components. 3.83× (lower ...
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... As shown in Fig. 1, source gate (denoted as S) and drain gate (denoted as D) connect with 3 vertically stacked silicon nanowires, and polarity gate at source (denoted as PGS) and polarity gate at the drain (PGD) close to the control gate (denoted as CG). There exist 4 states of this device, which is ON states, OFF states, low-leakage OFF states and uncertain states, and the detailed bias gate conditions are presented in [30]. More specifically, the two-inputs configuration of TIGFET can realize the complex Boolean logic (e.g. 2 series nFETs/pFETS and XOR), which reduces the area overhead compared with the CMOS devices. ...
In this paper, current mode logic based on the three-independent-gate field effect transistor (TIGFET) is introduced as the circuit-level side-channel attack (SCA) countermeasures, and a SCA-resilience flip-flop (DyCML) is designed to make the power consumption constant. Then, a simplified advanced encryption system (AES) is built, and power analysis is performed to evaluate the SCA-resistance efficacy. Simulation results show that the key with the TIGFET-based DyCML is not revealed with 255 power traces. The proposed design occupies less area usage and requires less delay overhead compared to the original TIGFET-based true single-phase clock (TSPC) and modified TSPC (mTSPC).
... In particular, these abilities include: (1) the dynamic reconfiguration of the polarity of the device (that is, the ability to choose if the channel carrier is effectively n-type or ptype) based on selective biasing of the Schottky gates [7], (2) the dynamic control of the threshold voltage (V t ) due to the dual switching mechanism of thermally-assisted tunneling through Schottky barriers or carrier transport similar to that in conventional MOSFETs [6], and (3) the dynamic control of the subthreshold slope due to a positive feedback induced by weak impact ionization [8]. While the TIGFET's independent control of its three gates allow for complex device-level operations and novel circuitlevel architectures [9][10][11][12][13][14][15]), the trade-off is that the two additional contacted gates required for the TIGFET's functionality boost will lead to an increase in the total device capacitance in comparison to a standard one-gate CMOS device. Thus, there is a need to study the TIGFETs' device-and circuitlevel capacitance in order to identify its capability at advanced technology nodes. ...
... The real benefit to using the functionality-enhanced TIGFET devices is at the gate-level. These benefits have been investigated in literature [9][10][11][12][13][14][15] and include the use of TIGFETs in circuit implementations of a dual-V T inverter, dual-V T NAND, 4-1 static multiplexer, 6T static randomaccess memory, true single phase clocking flip-flop, multiplexer, and power-gated differential cascade voltage switch logic. Of particular interest is the fact that a three-input XOR gate and a three-input MAJ gate can be realized using four TIGFET transistors (plus two and three inverters, respectively). ...
... These gate implementations are shown in Fig. 4 (b-c), along with the symbol representation of the device in Fig. 4-a. These circuit opportunities are only possible due to the polarity control characteristic of TIGFET technology that allows for higher-level circuit architecture to be designed [15]. ...
Three-Independent-Gate Field-Effect Transistors (TIGFETs) are a promising alternative technology that aims to replace or complement CMOS at advanced technology nodes. In this paper, we extracted the parasitic and intrinsic capacitances of a silicon-nanowire TIGFET device using three-dimensional numerical simulations in an attempt to accurately compare its capacitances and, consequently, circuit-level performances to CMOS at comparable nodes. Analytical models of the parasitic capacitances of a TIGFET transistor were derived using techniques such as the equivalent Schwarz-Christoffel transformation and standard cylindrical capacitors and show close agreement with numerical simulations. The maximum capacitance of a TIGFET transistor is 2× larger than for a 15 nm CMOS High Performance (HP) device due to the TIGFET’s two additional gated contacts, but this is countered by its ability for multiple modes of operation which reduces the effective switching capacitance per device. A TIGFET transistor sees, on average, only a 30% increase in total capacitance compared to a CMOS HP device. Additionally, the TIGFET’s increased device functionality can be used to modify the circuit-level architecture of a TIGFET-based design to mitigate the performance impact of its larger device-level capacitance. This combination of a TIGFET’s (1) multiple modes of operation, and (2) circuit-level architecture lead to enhanced system performance. In particular, we show that at the 15 nm technology node TIGFET technology has 18% lower energy-delay product for a fan-out of 4 and higher when using 1-bit full-adder logic circuit than for the equivalent node CMOS HP.
... In this context, industry and academia are looking for new computing and memory technologies and architectures that can enable both dense and energy efficient architectures. On one hand, Functionality Enhanced Devices (FED) such as Three Independent Gate Field Effect Transistors (TIGFET) [1] are perceived as a promising opportunity as they (i) are a direct evolution from FinFET technology and (ii) enable dense digital design thanks to their various functionalities such as polarity, sub-threshold slope and threshold voltage control [2]. On the other hand, emerging resistive memory technologies (RRAM) such as filamentary-based RRAM are already penetrating the market as they provide easy technology co-integration with MOS technologies, middle programming voltage and fast switching capabilities [3], [4]. ...
... Recent simulation studies have shown that scaling of device dimensions, as well as applying several stacked nanowires on top of each other [10], [41] will increase the device performance of SiNW RFETs significantly. Moreover, promising performance projections are given for both germanium nanowires as well as carbon nanotubes [4], [18], [42]- [44] making it conceivable that similar delay values as state-of-the art low-operationpower CMOS technology can be achieved. It should be noted that the real intrinsic delay value of an RFET technology is somewhere in the middle of an inverter circuit utilizing only low-leakage-type Schottky gates or high-performance channel gates (refer to Fig. 1). ...
An early evaluation in terms of circuit design is essential in order to assess the feasibility and practicability aspects for emerging nanotechnologies. Reconfigurable nanotechnologies, such as silicon or germanium nanowire-based reconfigurable field-effect transistors, hold great promise as suitable primitives for enabling multiple functionalities per computational unit. However, contemporary CMOS circuit designs when applied directly with this emerging nanotechnology often result in suboptimal designs. For example, 31% and 71% larger area was obtained for our two exemplary designs. Hence, new approaches delivering tailored circuit designs are needed to truly tap the exciting feature set of these reconfigurable nanotechnologies. To this effect, we propose six functionally enhanced logic gates based on a reconfigurable nanowire technology and employ these logic gates in efficient circuit designs. We carry out a detailed comparative study for a reconfigurable multifunctional circuit, which shows better normalized circuit delay (20.14%), area (32.40%), and activity as the power metric (40%) while exhibiting similar functionality as compared with the CMOS reference design. We further propose a novel design for a 1-bit arithmetic logic unit-based on silicon nanowire reconfigurable FETs with the area, normalized circuit delay, and activity gains of 30%, 34%, and 36%, respectively, as compared with the contemporary CMOS version.
... While CMOS scaling has promised higher performance and smaller area from last few decades, the reconfigurable behavior shown by these technologies can enable the circuit designers to pack more functions per computational unit. This leads to reduced delay (smaller critical paths [43]), area [56], and overall energydelay-product [48] for the entire circuit. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. ...
Several emerging reconfigurable technologies have been explored in recent years offering device level runtime reconfigurability. These technologies offer the freedom to choose between p- and n-type functionality from a single transistor. In order to optimally utilize the feature-sets of these technologies, circuit designs and storage elements require novel design to complement the existing and future electronic requirements. An important aspect to sustain such endeavors is to supplement the existing design flow from the device level to the circuit level. This should be backed by a thorough evaluation so as to ascertain the feasibility of such explorations. Additionally, since these technologies offer runtime reconfigurability and often encapsulate more than one functions, hardware security features like polymorphic logic gates and on-chip key storage come naturally cheap with circuits based on these reconfigurable technologies. This paper presents innovative approaches devised for circuit designs harnessing the reconfigurable features of these nanotechnologies. New circuit design paradigms based on these nano devices will be discussed to brainstorm on exciting avenues for novel computing elements.
Designing logic gates based on emerging technologies is necessary as they form the building block for digital design. It lays the foundation to enable EDA for the commercialization of such a technology. With the emergence of reconfigurable nanotechnology as one of the viable technology for future electronics, a crucial task is to formalize designs and topologies for various logic gates and circuits (Rai et al. (Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics? In: Proceedings of the International Conference on Computer-Aided Design. ICCAD ’18. San Diego, California: ACM, 13:1–13:8, 2018)).KeywordsDesign topologiesFunctionality-enhancedTSPC DFFALUMetastabilitySR-latch
Side-channel attack (SCA) reveals confidential information by statistically analyzing physical manifestations, which is the serious threat to cryptographic circuits. Various SCA circuit-level countermeasures have been proposed as fundamental solutions to reduce the side-channel vulnerabilities of cryptographic implementations; however, such approaches introduce non-negligible power and area overheads. Among all of the circuit components, flip-flops are the main source of information leakage. This article proposes a three-phase single-rail pulse register (TSPR) based on the three-independent-gate field effect transistor (TIGFET) to achieve all desired properties with improved metrics of area and security. TIGFET-based TSPR consumes a constant power (MCV is 0.25%), has a low delay (12 ps), and employs only 10 TIGFET devices, which is applicable for the low-overhead and high-security cryptographic circuit design compared to the existing flip-flops. In addition, a set of TIGFET-based combinational basic gates are designed to reduce the area occupation and power consumption as much as possible. As a proof of concept, a simplified advanced encryption algorithm (AES), SM4 block cipher algorithm (SM4), and light-weight cryptographic algorithm (PRESENT) are built with the TIGFET-based library. SCA is implemented on the cryptographic implementations to prove its SCA resilience, and the SCA results show that the correct key of cryptographic circuits with TIGFET-based TSPRs is not guessed within 2,000 power traces.
Side-channel attack (SCA) is one of the physical attacks, which will reveal the confidential information from cryptographic circuits by statistically analyzing physical manifestations. Various circuit-level countermeasures have been proposed as fundamental solutions to eliminate the correlations between side-channel information and circuit’s internal operations. The existing solutions, however, will introduce nonnegligible power and area overheads, making them difficult to be deployed in resource-constrained applications. In this article, a novel three-independent-gate silicon nanowire field effect transistor (TIGFET) with the intrinsic SCA-resilience characteristics is introduced to balance the tradeoffs among cost, performance, and security of cryptographic implementations. We construct six TIGFET-based current mode logic (CML) gates that can retain lower power variation under all possible transitions compared to the CMOS counterparts. As a proof of concept, advanced encryption standard (AES), SM4 block cipher algorithm (SM4), and lightweight cryptographic algorithm PRESENT are implemented utilizing the TIGFET-based CML gates. Correlation power attack is performed to evaluate the improvement of SCA resilience. Simulation results verify that the TIGFET-based cryptographic implementations decrease 42.37% area usage, lower 61.16% energy efficiency, reduce
$5.35\times $
power variation, and achieve a similar level of SCA resistance compared to the CMOS counterpart, which is applicable for the resource-constrained applications.
The operation of reconfigurable field effect transistor (RFET) is governed by Schottky barrier, ungated regions as well as control and polarity gates. The inherent architecture of RFET, apart from lowering the effective drain bias, impedes the use of existing mobility extraction methodologies. In this brief, we propose a simple and effective methodology to evaluate the resistance offered by various regions, ascertain the effective drain bias across the un-gated transistor, and extract apparent low field mobility and its degradation coefficients in RFET. The developed analytical expressions for drain current (
$I_{{DS}}$
) and transconductance (
$g_{{m}}$
) of RFET are able to accurately predict current (
$I_{DS}$
) - control gate (
$V_{CG}$
), and
$g_{m}-V_{CG}$
characteristics.
This paper presents a new structure of Dielectric Separated Independent Gates Junctionless Transistor (DSIG-JLT) with four independent gates. The proposed DSIG-JLT is used to implement area and power efficient digital circuits by optimizing structure of the device and circuit level logic. This paper includes the modeling, simulation and design overview of DSIG-JLT to analyze the behavior of the device. Physics based analytical model explains the working principle of DSIG-JLT. It has four independent gates which are electrically controlled in multiple ways to realize full functionality of NOT, NAND, NOR Gate and Half-adder circuit. ATLAS 3-D device simulator is used to verify the developed model.
